-
公开(公告)号：US20190393229A1
公开(公告)日：2019-12-26
申请号：US16404983
申请日：2019-05-07
IPC分类号： H01L27/1157 , H01L27/11575 , H01L29/423 , H01L21/28 , H01L21/033 , H01L29/06
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated into a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A first logic device comprises a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed on the first logic gate dielectric within the logic device trench. By arranging the first logic gate electrode within the logic device trench, metal layer loss and the resulted sheet resistance and threshold voltage variations and mismatch issues caused by the subsequent planarization process can be improved.
-
公开(公告)号：US11189628B2
公开(公告)日：2021-11-30
申请号：US16404983
申请日：2019-05-07
IPC分类号： H01L27/1157 , H01L27/11575 , H01L29/06 , H01L21/033 , H01L29/423 , H01L21/28
摘要： Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated into a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A first logic device comprises a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed on the first logic gate dielectric within the logic device trench. By arranging the first logic gate electrode within the logic device trench, metal layer loss and the resulted sheet resistance and threshold voltage variations and mismatch issues caused by the subsequent planarization process can be improved.
-
公开(公告)号：US10811426B2
公开(公告)日：2020-10-20
申请号：US16393159
申请日：2019-04-24
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11573 , H01L29/423 , H01L27/11568 , H01L29/51 , H01L29/66 , H01L21/28 , H01L27/11536
摘要： The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region disposed adjacent to the memory region. The memory region comprises a non-volatile memory (NVM) device having a control gate electrode and a select gate electrode disposed between two neighboring source/drain regions over a substrate. The control gate electrode and the select gate electrode comprise polysilicon. The logic region comprises a logic device including a metal gate electrode disposed between two neighboring source/drain regions over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.
-
公开(公告)号：US20200098778A1
公开(公告)日：2020-03-26
申请号：US16695505
申请日：2019-11-26
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11575 , H01L21/762 , H01L27/11573 , H01L21/76 , H01L29/06
摘要： In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices.
-
公开(公告)号：US20170345841A1
公开(公告)日：2017-11-30
申请号：US15167070
申请日：2016-05-27
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11573 , H01L21/28 , H01L29/51 , H01L21/311 , H01L29/423 , H01L27/11568 , H01L21/3213 , H01L21/321 , H01L29/66 , H01L29/49
CPC分类号： H01L27/11573 , H01L21/28273 , H01L21/28282 , H01L27/11536 , H01L27/11568 , H01L29/42328 , H01L29/42344 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region. A sacrificial logic gate electrode is formed within the logic region together with a control gate electrode or a select gate electrode within the memory region by patterning a control gate layer or a select gate layer. A first inter-layer dielectric layer is formed between the sacrificial logic gate electrode and the control gate electrode or the select gate electrode. A hard mask is formed over the first inter-layer dielectric layer to cover the memory region and to expose the sacrificial logic gate electrode within the logic region. The sacrificial logic gate electrode is replaced with a high-k gate dielectric layer and a metal layer to form a metal gate electrode within the logic region.
-
公开(公告)号：US11264402B2
公开(公告)日：2022-03-01
申请号：US16695505
申请日：2019-11-26
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11575 , H01L29/06 , H01L21/76 , H01L27/11573 , H01L21/762
摘要： In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of memory devices within an embedded memory region of a substrate and forming a plurality of transistor devices within a logic region of the substrate. A first isolation structure is formed within a boundary region of the substrate disposed between the logic region and the embedded memory region. The first isolation structure is formed within a recess in the substrate. A logic wall is formed over the first isolation structure. The logic wall surrounds the embedded memory region and has a first height that is greater than heights of the plurality of memory devices.
-
公开(公告)号：US11211388B2
公开(公告)日：2021-12-28
申请号：US16022702
申请日：2018-06-29
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H01L27/112 , H01L29/06 , H01L23/00 , H01L21/765 , H01L29/40 , H01L29/66 , H01L27/11534 , H01L21/762 , H01L27/11524 , H01L27/11546 , H01L21/28
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
-
公开(公告)号：US11177268B2
公开(公告)日：2021-11-16
申请号：US16584710
申请日：2019-09-26
发明人： Wei-Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11524 , H01L29/66 , H01L29/788
摘要： A memory device includes a substrate, a transistor, and a memory cell. The substrate includes a cell region and a logic region. The transistor is over the logic region and includes a first metal gate stack. The memory cell is over the cell region and includes an erase gate. The erase gate is a metal gate stack.
-
公开(公告)号：US20190252399A1
公开(公告)日：2019-08-15
申请号：US16393159
申请日：2019-04-24
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11573 , H01L27/11536 , H01L29/423 , H01L21/28 , H01L29/51 , H01L29/66 , H01L27/11568
CPC分类号： H01L27/11573 , H01L27/11536 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42328 , H01L29/42344 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a logic region disposed adjacent to the memory region. The memory region comprises a non-volatile memory (NVM) device having a control gate electrode and a select gate electrode disposed between two neighboring source/drain regions over a substrate. The control gate electrode and the select gate electrode comprise polysilicon. The logic region comprises a logic device including a metal gate electrode disposed between two neighboring source/drain regions over a logic gate dielectric and having bottom and sidewall surfaces covered by a high-k gate dielectric layer.
-
公开(公告)号：US20190035801A1
公开(公告)日：2019-01-31
申请号：US16033357
申请日：2018-07-12
发明人： Wei Cheng Wu , Chien-Hung Chang
IPC分类号： H01L27/11575 , H01L29/06
CPC分类号： H01L27/11575 , H01L21/76 , H01L21/76224 , H01L27/11573 , H01L29/0649
摘要： In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.024 秒)
