公开(公告)号：US11069419B2

公开(公告)日：2021-07-20

申请号：US16122104

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: H01L29/788 ,  G11C29/02 ,  H01L21/28 ,  G01R31/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/56 ,  H01L21/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

公开(公告)号：US20170133388A1

公开(公告)日：2017-05-11

申请号：US14933046

申请日：2015-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20170110202A1

公开(公告)日：2017-04-20

申请号：US14883791

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G11C29/02 ,  H01L23/528 ,  H01L29/51 ,  G01R31/26 ,  H01L27/115 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/544 ,  H01L29/49

CPC classification number: G01R31/2644 ,  H01L21/32133 ,  H01L21/76877 ,  H01L22/34 ,  H01L23/528 ,  H01L23/544 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L2223/54406 ,  H01L2223/54453 ,  H01L2223/5446

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed. The integrated chip has a semiconductor substrate. A test line letter is arranged over the semiconductor substrate. The test line letter comprises a positive relief that protrudes outward from the semiconductor substrate in the shape of an alpha-numeric character. One or more dummy structures are arranged over the semiconductor substrate. The one or more dummy structures are proximate to a boundary of the test line letter.

公开(公告)号：US11264400B2

公开(公告)日：2022-03-01

申请号：US16950144

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US10163522B2

公开(公告)日：2018-12-25

申请号：US14883787

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Tsung Lien ,  Fang-Lan Chu ,  Hong-Da Lin ,  Wei Cheng Wu ,  Ku-Ning Chang ,  Yu-Chen Wang

IPC: G02F1/1333 ,  H01L23/544 ,  G11C29/02 ,  G01R31/28 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/56 ,  H01L21/66

Abstract: The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate. A test line letter structure is arranged over the semiconductor substrate and has one or more trenches vertically extending between an upper surface of the test letter structure and a lower surface of the test line letter structure. The one or more trenches are arranged within the test line letter structure to form an opening in the upper surface of the test line structure that has a shape of an alpha-numeric character.

公开(公告)号：US20180219018A1

公开(公告)日：2018-08-02

申请号：US15938043

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20210074712A1

公开(公告)日：2021-03-11

申请号：US16950144

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US20200035692A1

公开(公告)日：2020-01-30

申请号：US16587246

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US10475805B2

公开(公告)日：2019-11-12

申请号：US16396963

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/108 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The channel region includes a first portion adjacent to the first source/drain region and a second portion adjacent the second source/drain region. A select gate is spaced over the first portion of the channel region and is separated from the first portion of the channel region by a select gate dielectric. A memory gate is spaced over the second portion of the channel region and is separated from the second portion of the channel region by a charge-trapping dielectric structure. The charge-trapping dielectric structure extends upwardly alongside the memory gate to separate neighboring sidewalls of the select gate and memory gate from one another. An oxide spacer or nitride-free spacer is arranged in a sidewall recess of the charge-trapping dielectric structure nearest the second source/drain region.

公开(公告)号：US10032786B2

公开(公告)日：2018-07-24

申请号：US15267954

申请日：2016-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Jui-Tsung Lien

IPC: H01L27/11 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11534 ,  H01L27/11548

Abstract: In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.