公开(公告)号：US20090194808A1

公开(公告)日：2009-08-06

申请号：US12362019

申请日：2009-01-29

申请人： Ryota FUJITSUKA ,  Yoshio Ozawa ,  Katsuaki Natori

发明人： Ryota FUJITSUKA ,  Yoshio Ozawa ,  Katsuaki Natori

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/112

摘要： A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge storage insulating film, and a control gate electrode formed on the block insulating film, wherein a distance between the element region and the control gate electrode is shorter at a center portion of the unit gate structure than at both ends thereof, as viewed in a section parallel to a channel width direction.

摘要翻译： 半导体器件包括具有沟道区域的元件区域和在沟道区域中引起沟道的单元栅极结构，所述单元栅极结构包括形成在元件区域上的隧道绝缘膜，形成在隧道绝缘层上的电荷存储绝缘膜 形成在电荷存储绝缘膜上的块绝缘膜和形成在块绝缘膜上的控制栅极电极，其中元件区域和控制栅电极之间的距离在单元栅极结构的中心部分较短 在与通道宽度方向平行的部分中看到的两端。

公开(公告)号：US20090004833A1

公开(公告)日：2009-01-01

申请号：US12146802

申请日：2008-06-26

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US20080261370A1

公开(公告)日：2008-10-23

申请号：US12155272

申请日：2008-06-02

申请人： Isao Kamioka ,  Yoshio Ozawa

发明人： Isao Kamioka ,  Yoshio Ozawa

IPC分类号： H01L21/336

CPC分类号： H01L29/40114 ,  H01L21/3247 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; annealing the second insulating film in a second processing chamber; and forming a second conductive layer on the second insulating film.

摘要翻译： 根据本发明，提供一种半导体器件制造方法，包括：在半导体衬底上形成第一绝缘膜; 在所述第一绝缘膜上形成第一导电层; 在与外部隔离的第一处理室中在所述第一导电层上形成第二绝缘膜; 对第一处理室中的第二绝缘膜执行修改处理，并将半导体衬底从第一处理室卸载到外部; 在第二处理室中退火第二绝缘膜; 以及在所述第二绝缘膜上形成第二导电层。

公开(公告)号：US07396721B2

公开(公告)日：2008-07-08

申请号：US11130128

申请日：2005-05-17

申请人： Isao Kamioka ,  Yoshio Ozawa

发明人： Isao Kamioka ,  Yoshio Ozawa

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/3247 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: forming a first insulating film on a semiconductor substrate; forming a first conductive layer on the first insulating film; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; annealing the second insulating film in a second processing chamber; and forming a second conductive layer on the second insulating film.

摘要翻译： 根据本发明，提供一种半导体器件制造方法，包括：在半导体衬底上形成第一绝缘膜; 在所述第一绝缘膜上形成第一导电层; 在与外部隔离的第一处理室中在所述第一导电层上形成第二绝缘膜; 对第一处理室中的第二绝缘膜执行修改处理，并将半导体衬底从第一处理室卸载到外部; 在第二处理室中退火第二绝缘膜; 以及在所述第二绝缘膜上形成第二导电层。

公开(公告)号：US07391076B2

公开(公告)日：2008-06-24

申请号：US11709160

申请日：2007-02-22

申请人： Yoshio Ozawa

发明人： Yoshio Ozawa

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7883

摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括设置在半导体衬底上的隧道绝缘膜，设置在隧道绝缘膜上的浮置栅电极， 所述浮栅电极的宽度在所述非易失性存储单元的沟道宽度或长度方向上在高度方向上变化，并且在所述浮栅电极的底表面之上的区域和其上表面之下的区域中最薄， 设置在所述控制栅电极和所述浮置栅电极之间的电极间绝缘膜。

公开(公告)号：US20070254434A1

公开(公告)日：2007-11-01

申请号：US11819428

申请日：2007-06-27

申请人： Ichiro Mizushima ,  Yoshio Ozawa

发明人： Ichiro Mizushima ,  Yoshio Ozawa

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate including an active area (AA) surrounded by an isolation insulating film, and a nonvolatile memory cell on the AA, the nonvolatile memory cell including a tunnel insulating film on the AA, a FG electrode on the tunnel insulating film, a CG electrode above the FG electrode, and an interelectrode insulating film between the FG electrode and the CG electrode, relating to a cross section in a channel width direction of the nonvolatile memory cell, dimension in the channel width direction of a top surface of the AA is shorter than dimension in the channel width direction of a bottom surface of the tunnel insulating film, and an area of a portion opposing the AA of the tunnel insulating film is smaller than an area of a portion opposing a top surface of the FG electrode of the interelectrode insulating film.

摘要翻译： 一种半导体器件包括：半导体衬底，包括由隔离绝缘膜包围的有源区（AA）和在AA上的非易失性存储单元，非易失性存储单元包括AA上的隧道绝缘膜，隧道绝缘上的FG电极 薄膜，FG电极上方的CG电极以及FG电极和CG电极之间的电极间绝缘膜，涉及非易失性存储单元的沟道宽度方向上的横截面，顶表面的沟道宽度方向上的尺寸 的距离短于隧道绝缘膜的底面的沟道宽度方向上的尺寸，并且与隧道绝缘膜的AA相对的部分的面积小于与隧道绝缘膜的顶面相对的部分的面积 电极间绝缘膜的FG电极。

公开(公告)号：US20070218605A1

公开(公告)日：2007-09-20

申请号：US11790033

申请日：2007-04-23

申请人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Yasumasa Suizu ,  Yoshitaka Tsunashima

IPC分类号： H01L21/765

CPC分类号： H01L29/7881 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28044 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833 ,  Y10S438/911 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S438/966

摘要： A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

公开(公告)号：US20070200168A1

公开(公告)日：2007-08-30

申请号：US11706999

申请日：2007-02-16

申请人： Yoshio Ozawa ,  Yoshitaka Tsunashima

发明人： Yoshio Ozawa ,  Yoshitaka Tsunashima

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234

摘要： A MONOS type nonvolatile memory cell is structured such that a laminated insulating film which is formed by sequentially laminating a tunnel insulating layer, a charge storage insulating layer, and a charge block insulating layer is provided on a convex curved surface portion of a semiconductor substrate, and a control gate electrode is further formed thereon. A thickness of the tunnel insulating layer is set to be 4 to 10 nm, and data writing/data erasing operations are carried out by making an F-N tunneling current flow in the tunnel insulating layer.

摘要翻译： 构造为在半导体衬底的凸曲面部分上设置通过依次层叠隧道绝缘层，电荷存储绝缘层和电荷块绝缘层而形成的叠层绝缘膜的MONOS型非易失性存储单元， 并且还在其上形成控制栅电极。 将隧道绝缘层的厚度设定为4〜10nm，通过在隧道绝缘层中形成F-N隧道电流来进行数据写入/数据擦除动作。

公开(公告)号：US07183615B2

公开(公告)日：2007-02-27

申请号：US10868773

申请日：2004-06-17

申请人： Hiroki Yamashita ,  Yoshio Ozawa ,  Atsuhiro Sato

发明人： Hiroki Yamashita ,  Yoshio Ozawa ,  Atsuhiro Sato

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324 ,  Y10T428/24256

摘要： A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.

摘要翻译： 半导体存储器具有存储单元阵列，其包括（a）沿着列方向延伸的器件隔离膜，交替地布置在沿着行方向排列的存储单元晶体管之间，（b）沿行和列方向排列的第一导电层 第一导电层的顶表面位于比器件隔离膜的顶表面更低的水平面上，（c）布置在器件隔离膜和第一导电层上的电极间电介质，使得电极间电介质可以 由属于不同单元列的存储单元晶体管所共用，电极间电介质的相对介电常数高于器件隔离膜的相对介电常数，（d）沿着行方向延伸的第二导电层， 在电极间电介质上。 这里，器件隔离膜的上角被倒角。

公开(公告)号：US07109549B2

公开(公告)日：2006-09-19

申请号：US10986074

申请日：2004-11-12

申请人： Yoshio Ozawa

发明人： Yoshio Ozawa

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336

摘要： Disclosed is a semiconductor device having a plurality of memory cells arranged in a first direction and a second direction perpendicular to the first direction, each memory cell comprising a first insulating film formed on a semiconductor substrate, a floating gate formed on the first insulating film, a second insulating film which includes a first portion formed on a top surface of the floating gate and a second portion formed on that side surface of the floating gate which is parallel to the first direction, and a control gate which covers the first and second portions of the second insulating film, a width in the second direction of the floating gate increasing with increasing distance from its bottom, and a width in the second direction of the second portion of the second insulating film decreasing with increasing distance from its bottom.