公开(公告)号：US07586331B2

公开(公告)日：2009-09-08

申请号：US11482524

申请日：2006-07-07

申请人： Michele La Placa ,  Ignazio Martines

发明人： Michele La Placa ,  Ignazio Martines

IPC分类号： H03K19/094 ,  H03K17/16 ,  H03B1/00

CPC分类号： H03K19/00384 ,  H03K17/167

摘要： A self-adaptive output buffer for an output terminal of an electronic circuit suitable to be connected to a load is proposed. The self-adaptive output buffer includes means for sensing an indication of the capacitance of the load and means for driving the load according to the sensing, wherein the means for sensing includes capacitive means with a preset capacitance, means for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring a measuring voltage at the capacitive means due to a charge sharing between the capacitive means and the load.

摘要翻译： 提出了适用于连接到负载的电子电路的输出端的自适应输出缓冲器。 自适应输出缓冲器包括用于感测负载的电容的指示的装置和根据感测来驱动负载的装置，其中用于感测的装置包括具有预设电容的电容装置，用于将电容装置充电到 预置电压，用于将充电的电容装置与负载耦合的装置，以及由于电容装置和负载之间的电荷共享而在电容装置处测量测量电压的装置。

公开(公告)号：US20090195522A1

公开(公告)日：2009-08-06

申请号：US12362882

申请日：2009-01-30

申请人： Kenji Shino ,  Yasukazu Noine

发明人： Kenji Shino ,  Yasukazu Noine

IPC分类号： G09G5/00

CPC分类号： G09G3/22 ,  G09G3/2014 ,  G09G2300/0465 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/025 ,  G09G2330/028 ,  H03K17/167

摘要： A drive circuit for driving a display panel having wirings and display devices to be connected to the wirings, has a first switch that transits potential of the wirings toward the first potential, a feedback amplifier that maintains the potentials of the wirings at the first potential, and a second switch that selects whether or not to supply an output from the feedback amplifier to the wirings. The first switch and the second switch are connected to the wirings in parallel. A drive performance of the first switch is lower than that of the feedback amplifier. As a result, stable driving waveforms can be output in a simple and inexpensive circuit configuration.

摘要翻译： 用于驱动具有布线的显示面板和要连接到布线的显示装置的驱动电路具有使配线的电位朝向第一电位的第一开关，将布线的电位维持在第一电位的反馈放大器， 以及第二开关，其选择是否将来自反馈放大器的输出提供给布线。 第一开关和第二开关并联连接到布线。 第一开关的驱动性能低于反馈放大器的驱动性能。 结果，可以以简单且廉价的电路配置输出稳定的驱动波形。

公开(公告)号：US07368898B2

公开(公告)日：2008-05-06

申请号：US11080829

申请日：2005-03-15

申请人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

发明人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

IPC分类号： G05F1/40 ,  G05F1/56 ,  H02M1/12

CPC分类号： H02M3/157 ,  H02M1/088 ,  H02M1/38 ,  H02M3/158 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/0025 ,  H02M2001/0048 ,  H03K5/1565 ,  H03K17/122 ,  H03K17/167 ,  H03K17/6871 ,  Y02B70/1466 ,  Y02B70/1491

摘要： A method of sensing current in an output regulator comprises providing a current sensor having a gain resolution, setting the current sensor gain resolution to an initial resolution, sensing a current flowing through the current sensor, evaluating an amplitude of the current, and at a sampling frequency, controlling the gain resolution of the current sensor based on the evaluating.

摘要翻译： 感测输出调节器中的电流的方法包括提供具有增益分辨率的电流传感器，将电流传感器增益分辨率设置为初始分辨率，感测流过电流传感器的电流，评估电流的幅度，以及采样 频率，基于评估控制电流传感器的增益分辨率。

公开(公告)号：US20080030176A1

公开(公告)日：2008-02-07

申请号：US11906087

申请日：2007-09-28

申请人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

发明人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

IPC分类号： G05F1/59

CPC分类号： H02M3/157 ,  H02M1/088 ,  H02M1/38 ,  H02M3/158 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/0025 ,  H02M2001/0048 ,  H03K5/1565 ,  H03K17/122 ,  H03K17/167 ,  H03K17/6871 ,  Y02B70/1466 ,  Y02B70/1491

摘要： A method of controlling deadtime between power switches in an output regulator includes providing at least two power switches having a common node, wherein at least one of the two power switches is a conducting switch and a remainder of the two power switches is a free-wheeling switch, switching one of the conducting switch and the free-wheeling switch from an on-state to an off-state, during a transition from the on-state to the off-state, monitoring a current flowing through one of the conducting switch and the free-wheeling switch, comparing the current to a reference level, and delaying for a predetermined time period, then changing the operating state of the other of the conducting switch and the freewheeling switch from an off-state to an on-state.

摘要翻译： 一种控制输出调节器中的电源开关之间的死区时间的方法，包括提供具有公共节点的至少两个功率开关，其中两个功率开关中的至少一个是导通开关，并且两个功率开关的其余部分是续流 开关，其中一个导通开关和续流开关从导通状态切换到截止状态，在从导通状态转换到截止状态时，监视流过导通开关之一的电流， 续流开关，将电流与参考电平进行比较，并延迟预定时间段，然后将导通开关和续流开关中的另一个的运行状态从截止状态改变为导通状态。

公开(公告)号：US20070176649A1

公开(公告)日：2007-08-02

申请号：US11619819

申请日：2007-01-04

申请人： Michael Hausmann

发明人： Michael Hausmann

IPC分类号： H03B1/00

CPC分类号： H03K19/00323 ,  H03K17/167 ,  H03K19/00384

摘要： A method and integrated circuit for the transmission of differential signals with a signal and a complementary signal is disclosed. For trimming the edge steepness of the signal with that of the complementary signal, the integrated circuit has a first driver for generating the signal, and a second driver for generating the complementary signal. A circuit is provided, configured to control the edge steepness of the signal or of the complementary signal.

摘要翻译： 公开了一种用于传输具有信号和互补信号的差分信号的方法和集成电路。 为了修整信号的边缘陡度与互补信号的边缘陡度，集成电路具有用于产生信号的第一驱动器和用于产生互补信号的第二驱动器。 提供了一种电路，被配置为控制信号或互补信号的边缘陡度。

公开(公告)号：US20070063730A1

公开(公告)日：2007-03-22

申请号：US11601263

申请日：2006-11-17

申请人： Girolamo Gallo ,  Giulio Marotta

发明人： Girolamo Gallo ,  Giulio Marotta

IPC分类号： H03K17/16

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/018585

摘要： An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

摘要翻译： 用于半导体存储器件和其它半导体器件的输出缓冲器包括反馈电路，以响应于各种负载条件来动态地控制输出缓冲器的输出阻抗，从而减少输出振铃。 输出缓冲器还可以包括用于支持选择性地转换器件以在各种电源电压范围进行操作的电路，而不需要额外的掩模或处理步骤。

公开(公告)号：US07161376B2

公开(公告)日：2007-01-09

申请号：US11358235

申请日：2006-02-21

申请人： Girolamo Gallo ,  Giulio Marotta

发明人： Girolamo Gallo ,  Giulio Marotta

IPC分类号： H03K19/0175

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/018585

摘要： An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

公开(公告)号：US07098704B2

公开(公告)日：2006-08-29

申请号：US10860482

申请日：2004-06-04

申请人： Masahiro Ikezaki

发明人： Masahiro Ikezaki

IPC分类号： H03B1/00

CPC分类号： H03K17/167 ,  H03K17/164

摘要： A semiconductor integrated circuit device with a buffer circuit is disclosed, which comprises a pre-buffer configured to receive an input signal from a front-stage circuit, a drive buffer having a first PMOS transistor and a first NMOS transistor connected in series between a power supply node and a ground node, the first PMOS and NMOS transistors having gates for receiving an output signal of the pre-buffer, a series-connection node of the first PMOS and NMOS transistors being connected to the output node, and a back-up buffer having a second PMOS transistor and a second NMOS transistor connected in series between the power supply node and the ground node, a series-connection node of the second PMOS and NMOS transistors being connected to the output node, one of the second PMOS and NMOS transistors is turned on after the other is turned off when the drive buffer is in a switching operation.

摘要翻译： 公开了一种具有缓冲电路的半导体集成电路器件，其包括预缓冲器，其被配置为从前级电路接收输入信号，驱动缓冲器具有第一PMOS晶体管和第一NMOS晶体管，串联连接在电源 电源节点和接地节点，第一PMOS和NMOS晶体管具有用于接收预缓冲器的输出信号的栅极，第一PMOS的串联连接节点和连接到输出节点的NMOS晶体管，以及备用 缓冲器，具有串联连接在电源节点和接地节点之间的第二PMOS晶体管和第二NMOS晶体管，第二PMOS和NMOS晶体管的串联连接节点连接到输出节点，第二PMOS和NMOS之一 当驱动缓冲器处于切换操作时，晶体管在另一个断开之后导通。

公开(公告)号：US07053660B2

公开(公告)日：2006-05-30

申请号：US11121130

申请日：2005-05-04

申请人： Kunihiro Itoh ,  Osamu Uno

发明人： Kunihiro Itoh ,  Osamu Uno

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/00361 ,  H03K17/167

摘要： An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

摘要翻译： 输出缓冲器包括接收具有尖锐波形的输入信号的第一驱动电路，并产生具有平缓波形的输出信号。 第二驱动电路在输出端子处连接到第一驱动电路，并且具有比第一驱动电路低的阻抗。 延迟电路也连接到输出端子并产生延迟的输出信号。 第一控制电路连接在延迟电路和第二驱动电路之间，并接收输入信号和延迟的输出信号，并产生用于驱动第二驱动电路的第一控制信号。

公开(公告)号：US07053594B2

公开(公告)日：2006-05-30

申请号：US10827645

申请日：2004-04-19

申请人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

发明人： Sehat Sutardja ,  Runsheng He ,  Jiancheng Zhang

IPC分类号： G05F1/40

CPC分类号： H02M3/157 ,  H02M1/088 ,  H02M1/38 ,  H02M3/158 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/0025 ,  H02M2001/0048 ,  H03K5/1565 ,  H03K17/122 ,  H03K17/167 ,  H03K17/6871 ,  Y02B70/1466 ,  Y02B70/1491

摘要： A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator. The output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output. The duty cycle limiter including a digital controller to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle. The digital controller to control the reference level at a frequency at least equal to a switching frequency of the output regulator. The digital controller to limit the computed duty cycle to the maximum duty cycle.

摘要翻译： 用于限制输入调节器的输入源和调节输出之间的能量传递的占空比限制器。 输出调节器具有调节器特性和计算的占空比，用于控制输入源和调节输出之间的能量传递。 占空比限制器包括数字控制器以产生参考电平并将输出调节器的调节器特性与参考电平进行比较以确定最大占空比。 数字控制器以至少等于输出调节器的开关频率的频率来控制参考电平。 数字控制器将计算出的占空比限制在最大占空比。