利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

28 条记录 (耗时 0.014 秒)

    Low power multiple bit sense amplifier
    1.
    发明授权
    Low power multiple bit sense amplifier 有权

    公开(公告)号：US07440332B2

    公开(公告)日：2008-10-21

    申请号：US11958658

    申请日：2007-12-18

    申请人： Girolamo Gallo ,  Giulio G. Marotta

    发明人： Girolamo Gallo ,  Giulio G. Marotta

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    LOW POWER MULTIPLE BIT SENSE AMPLIFIER
    2.
    发明申请
    LOW POWER MULTIPLE BIT SENSE AMPLIFIER 有权
    低功率多位感应放大器

    公开(公告)号：US20080094909A1

    公开(公告)日：2008-04-24

    申请号：US11958658

    申请日：2007-12-18

    申请人： Girolamo Gallo ,  Giulio Marotta

    发明人： Girolamo Gallo ,  Giulio Marotta

    IPC分类号： G11C16/06

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    摘要翻译： 用于多级闪存单元的读出放大器包括产生斜坡电压信号的电压斜坡发生器。 参考读出放大器将输入参考电流与斜坡电压信号产生的斜坡电流进行比较。 当斜坡电压信号大于参考电流时，输出锁存信号被切换。 读出放大器将输入位线电流与阈值进行比较，并在位线电流超过阈值时输出逻辑低电平。 读出放大器输出在锁存信号确定的时间被锁存在三个数字锁存器之一中。 编码器将来自三个数字锁存器的数据编码为两位输出数据。

    Variable impedence output buffer
    4.
    发明申请
    Variable impedence output buffer 有权

    公开(公告)号：US20060139051A1

    公开(公告)日：2006-06-29

    申请号：US11358235

    申请日：2006-02-21

    申请人： Girolamo Gallo ,  Giulio Marotta

    发明人： Girolamo Gallo ,  Giulio Marotta

    IPC分类号： H03K19/003

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/018585

    摘要： An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

    Low power multiple bit sense amplifier
    8.
    发明授权
    Low power multiple bit sense amplifier 有权
    低功率多位读出放大器

    公开(公告)号：US07324381B2

    公开(公告)日：2008-01-29

    申请号：US11416672

    申请日：2006-05-03

    申请人： Girolamo Gallo ,  Giulio G. Marotta

    发明人： Girolamo Gallo ,  Giulio G. Marotta

    IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/32

    摘要： A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.

    摘要翻译： 用于多级闪存单元的读出放大器包括产生斜坡电压信号的电压斜坡发生器。 参考读出放大器将输入参考电流与斜坡电压信号产生的斜坡电流进行比较。 当斜坡电压信号大于参考电流时，输出锁存信号被切换。 读出放大器将输入位线电流与阈值进行比较，并在位线电流超过阈值时输出逻辑低电平。 读出放大器输出在锁存信号确定的时间被锁存在三个数字锁存器之一中。 编码器将来自三个数字锁存器的数据编码为两位输出数据。

    Variable impedance output buffer
    9.
    发明授权
    Variable impedance output buffer 有权
    可变阻抗输出缓冲器

    公开(公告)号：US07271620B2

    公开(公告)日：2007-09-18

    申请号：US11601263

    申请日：2006-11-17

    申请人： Girolamo Gallo ,  Giulio Marotta

    发明人： Girolamo Gallo ,  Giulio Marotta

    IPC分类号： H03K19/0175

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K17/167 ,  H03K19/018585

    摘要： An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the output buffer in response to a variety of load conditions, thus reducing output ringing. The output buffer may also include circuitry to support selectively converting the device for operation at a variety of supply voltage ranges without the need for additional mask or process steps.

    摘要翻译： 用于半导体存储器件和其它半导体器件的输出缓冲器包括反馈电路，以响应于各种负载条件来动态地控制输出缓冲器的输出阻抗，从而减少输出振铃。 输出缓冲器还可以包括用于支持选择性地转换器件以在各种电源电压范围进行操作的电路，而不需要额外的掩模或处理步骤。

    Fast sensing scheme for floating-gate memory cells
    10.
    发明授权
    Fast sensing scheme for floating-gate memory cells 有权
    浮栅存储器单元的快速感测方案

    公开(公告)号：US07206240B2

    公开(公告)日：2007-04-17

    申请号：US10787911

    申请日：2004-02-25

    申请人： Girolamo Gallo ,  Tommaso Vali ,  Giulio Giuseppe Marotta

    发明人： Girolamo Gallo ,  Tommaso Vali ,  Giulio Giuseppe Marotta

    IPC分类号： G11C7/02

    CPC分类号： G11C7/04 ,  G11C7/14 ,  G11C16/24 ,  G11C16/26

    摘要： Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The sensing circuits further include a second precharging path for applying a second precharge potential to a target global bit line for precharging bit lines prior to sensing the programmed state of the floating-gate memory cell. The second precharging path is activated during only a portion of the precharging phase of a sensing operation to bring the bit lines rapidly up toward an asymptotic potential level. The second precharging path is thus deactivated prior to deactivating the first precharging path.

    摘要翻译： 感测电路适于更快地感测浮栅存储器单元的编程状态。 感测电路包括用于将第一预充电电位施加到感测装置的输入节点的第一预充电路径，用于在感测浮栅存储器单元的编程状态之前对位线进行预充电。 感测电路还包括第二预充电路径，用于在感测浮栅存储器单元的编程状态之前，将第二预充电电位施加到目标全局位线用于预充电位线。 第二预充电路径仅在感测操作的预充电阶段的一部分期间被激活，以使位线快速向上渐近的电位电平。 因此在停用第一预充电路径之前停用第二预充电路径。