公开(公告)号：US5548713A

公开(公告)日：1996-08-20

申请号：US272893

申请日：1994-07-08

申请人： Keith L. Petry ,  Thomas S. Hirsch ,  James W. Keeley

发明人： Keith L. Petry ,  Thomas S. Hirsch ,  James W. Keeley

IPC分类号： G06F11/22 ,  G06F11/00

CPC分类号： G06F11/2273 ,  G06F11/22

摘要： A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.

摘要翻译： 处理单元耦合到系统总线并且包括紧密耦合到本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元分别存储在第一和第二分离区域中，车载诊断（OBD）程序和引导程序。 OBD例程被组织成多个类别或阶段。 处理单元包括只能由微处理器访问的寄存器，在OBD程序的控制下，在每个单独的OBD程序的开始处加载多个预定值，用于识别要执行的特定阶段和次级测试。 连接到寄存器的装置被直接连接以显示寄存器的内容的第一相位部分，用于指示在发生故障的测试阶段。 寄存器的相位和相位内容用于识别失败的实际测试。 该信息为测试字典提供索引，该索引指示失败的组件的特定组件或组。

公开(公告)号：US5495591A

公开(公告)日：1996-02-27

申请号：US906618

申请日：1992-06-30

申请人： Charles P. Ryan

发明人： Charles P. Ryan

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6026 ,  Y10S707/99936

摘要： For a data processing system which employs a cache memory, the disclosure includes both a method for lowering the cache miss ratio for requested operands and an example of special purpose apparatus for practicing the method. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same, indicating a pattern which yields information which can be combined with an address in the stack to develop a predictive address. The efficiency of the apparatus is improved by placing a series of "select pattern" values representing the search order for trying patterns into a register stack and providing logic circuitry by which the most recently found "select pattern" value is placed at the top of the stack with the remaining "select pattern" values pushed down accordingly.

摘要翻译： 对于采用高速缓冲存储器的数据处理系统，本公开包括用于降低所请求的操作数的高速缓存未命中率的方法和用于实施该方法的专用设备的示例。 最近的高速缓存未命中被存储在先入先出的堆栈中，并且存储的地址被搜索到位移模式。 然后，通过从主存储器预取由预测地址识别的信号，随后采用任何检测到的模式来预测随后的高速缓存未命中。 用于执行该任务的装置优选地是为了速度目的而进行硬连接的，并且包括用于评估未命令堆栈中的各种移位地址的减法电路和用于确定来自至少两个减法电路的输出是否相同的比较器电路，指示产生信息的模式 其可以与栈中的地址组合以开发预测地址。 通过将表示用于尝试图案的搜索顺序的一系列“选择图案”值放置到寄存器堆栈中并提供逻辑电路来改善装置的效率，通过该逻辑电路将最近发现的“选择图案”值放置在 堆栈与剩余的“选择模式”值相应地下推。

公开(公告)号：US5394555A

公开(公告)日：1995-02-28

申请号：US993884

申请日：1992-12-23

申请人： John C. Hunter ,  John A. Wertz

发明人： John C. Hunter ,  John A. Wertz

IPC分类号： G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F12/00

CPC分类号： G06F12/0813

摘要： A computer cluster architecture including a plurality of CPUs at each of a plurality of nodes. Each CPU has the property of coherency and includes a primary cache. A local bus at each node couples: all the local caches, a local main memory having physical space assignable as-shared space and non-shared space and a local external coherency unit (ECU). An inter-node communication bus couples all the ECUs. Each ECU includes a monitoring section for monitoring the local and inter-node busses and a coherency section for a) responding to a non-shared cache-line request appearing on the local bus by directing the request to the non-shared space of the local memory and b) responding to a shared cache-line request appearing on the local bus by examining its coherence state to further determine if inter-node action is required to service the request and, if such action is required, transmitting a unique identifier and a coherency command to all the other ECUs. Each unit of information present in the shared space of the local memory is assigned, by the local ECU, a coherency state which may be: exclusive (the local copy of the requested information is unique in the cluster); 2) modified (the local copy has been updated by a CPU in the same node); 3) invalid (a local copy either does not exist or is known to be out-of-date); or 4) shared (the local copy is one of a plurality of current copies present in a plurality of nodes).

摘要翻译： 一种计算机集群架构，其包括在多个节点中的每一个处的多个CPU。 每个CPU都具有一致性的属性，并包含一个主缓存。 每个节点处的本地总线耦合：所有本地高速缓存，具有可分配空间和非共享空间的物理空间的本地主存储器和本地外部一致性单元（ECU）。 节点间通信总线耦合所有ECU。 每个ECU包括用于监视本地和节点间总线的监视部分和一个一致性部分，用于a）通过将请求引导到本地的非共享空间来响应出现在本地总线上的非共享高速缓存行请求 存储器和b）通过检查其相干状态来响应出现在本地总线上的共享高速缓存行请求，以进一步确定是否需要节点间动作来服务请求，并且如果需要这样的动作，则发送唯一的标识符和 一致命令给所有其他ECU。 存在于本地存储器的共享空间中的每个信息单元由本地ECU分配一个一致性状态，该状态可以是：排他（所请求的信息的本地副本在集群中是唯一的）; 2）修改（本地副本已由同一节点中的CPU更新）; 3）无效（本地副本不存在或已知过时）; 或4）共享（本地副本是存在于多个节点中的多个当前副本之一）。

公开(公告)号：US5367697A

公开(公告)日：1994-11-22

申请号：US781513

申请日：1991-10-22

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F1/30

CPC分类号： G06F11/1441

摘要： A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.

摘要翻译： 多处理器计算机系统包括第一处理器，第二处理器，用于执行系统管理功能的系统管理装置，包括检测待处理的电源关闭，以及发送寻址到每个第一处理器的停电功率停止消息， 以及用于在第一和第二处理器与系统管理装置之间进行通信的系统总线，包括待处理的电力关闭消息的通信。 第一处理器包括响应于等待的电源关闭消息的中断处理装置，用于执行电源关闭例程，以在电源终止之前将第一处理器置于已知状态，但是第二处理器固有地不包括电源关闭功能。 在每个第二处理器中，提供电源关闭装置以在电源终止之前将第二处理器置于已知状态，包括从系统总线连接的总线监视器，并且响应于任何电源关闭消息 第一处理器，用于产生指示向第一处理器发出电力关闭消息的输出。 第二处理器还包括从总线监视器的电源关闭消息输出连接的不可屏蔽中断逻辑，并且响应于总线监视器的电源关闭消息输出，以产生对第二处理器的不可屏蔽中断输出。 第二处理器又响应于不可屏蔽逻辑的不可屏蔽中断输出，用于查询不可屏蔽逻辑以确定中断的性质，并且响应于所指示的电力关闭消息发生到任何 第一处理器，用于在电源结束之前执行用于将第二处理器置于已知状态的电源关闭程序。

公开(公告)号：US5345573A

公开(公告)日：1994-09-06

申请号：US771702

申请日：1991-10-04

申请人： Raymond D. Bowden, III ,  Chester M. Nibby, Jr.

发明人： Raymond D. Bowden, III ,  Chester M. Nibby, Jr.

IPC分类号： G06F12/08 ,  G06F13/28 ,  G11C11/408 ,  G06F12/00 ,  G11C11/409

CPC分类号： G06F13/28 ,  G06F12/0879

摘要： A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.

摘要翻译： 耦合到微处理器的本地总线的存储器系统包括至少一对动态随机存取存储器（DRAM），并且包括用于在每个突发操作开始时存储地址序列的第一地址的电路，并且使用预定位来产生任何 作为这些位的状态的函数的一组地址序列中的一个。 第一预定地址位被用于选择由该对DRAM传送给用户的寻址读出数据字的不同序列。 对第二预定地址位进行补码，以反转具有特定地址序列的两个低阶寻址字响应的两个高阶寻址字应答。 这些操作在不同子组中的所有必需地址序列中使用。

公开(公告)号：US5341508A

公开(公告)日：1994-08-23

申请号：US771289

申请日：1991-10-04

申请人： James W. Keeley ,  Thomas F. Joyce

发明人： James W. Keeley ,  Thomas F. Joyce

IPC分类号： G06F13/40 ,  G06F15/80 ,  G06F13/42 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/4027 ,  G06F15/8015

摘要： A processing unit tightly couples to a system bus and includes a local memory which is accessible from such bus. The processing unit includes a high performance microprocessor which tightly couples to the local memory through a high speed synchronous bus shared with a plurality of synchronous state machines. A microprocessor internal bus state machine and the plurality of state machines control local bus accesses for transferring commands generated by the microprocessor and commands transferred from the system bus under the control of an external state machine for execution by a local memory state machine and the processor state machine, respectively, which also couples to the system bus.

摘要翻译： 处理单元紧密地耦合到系统总线并且包括可以从这种总线访问的本地存储器。 处理单元包括通过与多个同步状态机共享的高速同步总线紧密耦合到本地存储器的高性能微处理器。 微处理器内部总线状态机和多个状态机控制本地总线访问以传送由微处理器产生的命令和在外部状态机的控制下从系统总线传送的命令，以便由本地存储器状态机和处理器状态执行 机器，分别也耦合到系统总线。

公开(公告)号：US5287453A

公开(公告)日：1994-02-15

申请号：US584544

申请日：1990-09-18

申请人： William F. Roberts

发明人： William F. Roberts

IPC分类号： G06F9/46 ,  H04L12/24 ,  H04L12/44 ,  G06F13/00

CPC分类号： G06F9/547 ,  H04L12/24 ,  H04L41/00

摘要： A cluster computer system includes a plurality of independently operated computer systems located in close proximity to each other. Each system includes a system bus, a memory, and a set of local peripheral devices which connect in common to the system bus. The computer systems are interconnected for transferring messages to each other through the channels of a high speed cluster controller which connect to the system buses. Each system further includes a cluster driver which transfers the messages between the memory of the computer system and the corresponding cluster controller channel when the system is configured to operate in a cluster mode of operation. User application programs issue monitor calls to access files contained on a peripheral device(s). The fast remote file access (FRFA) facility included in each system upon detecting that the peripheral device is not locally attached, packages the monitor call and information identifying the user application into a message. The message is transferred through the cluster driver and cluster controller to the FRFA of the computer system to which the peripheral device attaches. The monitor call is executed and the response is sent back through the cluster controller and delivered to the user application in a manner so that the peripheral device of the other computer systems appears to be locally attached and the monitor call appears to be locally executed.

摘要翻译： 集群计算机系统包括彼此靠近定位的多个独立操作的计算机系统。 每个系统包括系统总线，存储器和一组共同连接到系统总线的本地外围设备。 计算机系统被互连以通过连接到系统总线的高速集群控制器的信道彼此传送消息。 每个系统还包括集群驱动器，当系统被配置为以集群操作模式操作时，该群集驱动器在计算机系统的存储器与相应的集群控制器通道之间传送消息。 用户应用程序发出监控呼叫以访问外围设备上包含的文件。 在检测到外围设备未本地连接时，每个系统中包括的快速远程文件访问（FRFA）功能，将监视器呼叫和识别用户应用程序的信息打包到消息中。 该消息通过集群驱动程序和集群控制器传输到外围设备附加到的计算机系统的FRFA。 监视器呼叫被执行，并且响应通过集群控制器发送回并以一种方式传送到用户应用程序，使得其他计算机系统的外围设备看起来是本地连接的，并且监视呼叫似乎在本地执行。

公开(公告)号：US5283887A

公开(公告)日：1994-02-01

申请号：US629926

申请日：1990-12-19

申请人： Leon Zachery

发明人： Leon Zachery

IPC分类号： G06F17/22 ,  G06Q10/10 ,  H04L12/58 ,  G06F5/00 ,  G06F13/00

CPC分类号： H04L12/5835 ,  G06F17/2264 ,  G06Q10/107 ,  H04L51/066

摘要： In a data processing system having an electronic mail system for sending documents from a first user to a recipient user and, for each user, a means for creating and editing documents, the documents having differing formats, a method for converting a document having a first format into a document having a second format preferred by the recipient user, using a table of user document format preferences and a document format conversion facility. The user preference table contains, for each user, an entry specifying the document format preferred by the user, and appended to each document to be sent to a recipient user is a tag which includes a field specifying the user to receive the document, and a field specifying the first format of the document. The document format field of the tag of a received document is compared with the preferred document format field of the user preference table entry of the recipient user, and, in response to a difference between the first format and the preferred format, the document conversion facility is used to convert the document from the first format to the preferred format.

摘要翻译： 在具有用于从第一用户发送文档到接收者用户的电子邮件系统的数据处理系统中，并且对于每个用户，用于创建和编辑文档的装置，具有不同格式的文档，用于转换具有第一 使用用户文档格式偏好表和文档格式转换设备，格式化成具有接收者用户优选的第二格式的文档。 对于每个用户，用户偏好表包含指定用户优选的文档格式的条目，并且附加到要发送给收件人用户的每个文档的标签是包括指定用户以接收文档的字段的标签，以及 字段指定文档的第一个格式。 将接收到的文档的标签的文档格式字段与接收用户的用户偏好表条目的优选文档格式字段进行比较，并且响应于第一格式和优选格式之间的差异，文档转换设备 用于将文档从第一格式转换为首选格式。

公开(公告)号：US5278984A

公开(公告)日：1994-01-11

申请号：US629873

申请日：1990-12-19

申请人： Richard E. Batchelor

发明人： Richard E. Batchelor

IPC分类号： H04L12/58 ,  G06F7/06 ,  G06F13/18

CPC分类号： H04L51/26 ,  H04L51/30

摘要： A queue manager for controlling the execution of requests for the transport of messages from users to destinations. Each request includes a message and an identification of a destination. The queue manager includes a queue for storing pending requests and a dispatcher task for creating a worker task to execute each request and provides a method for adapting the execution of requests to constraints and characteristics of destinations and communications links.

摘要翻译： 一个队列管理器，用于控制从用户到目的地的邮件传输请求的执行。 每个请求包括消息和目的地的标识。 队列管理器包括用于存储未决请求的队列和用于创建工作任务以执行每个请求的分派器任务，并且提供用于使请求执行适应目的地和通信链路的约束和特征的方法。

公开(公告)号：US5276738A

公开(公告)日：1994-01-04

申请号：US992210

申请日：1992-12-17

申请人： Thomas S. Hirsch

发明人： Thomas S. Hirsch

IPC分类号： G06F12/14 ,  H04L9/00 ,  H04L9/02

CPC分类号： G06F12/1408 ,  H04L9/0869

摘要： A protection mechanism includes means for taking an input binary value and generating a unique key value as well as performing the reverse operation of taking a key value and generating an input binary value. The mechanism includes a scrambler which includes an array having a number of multibit container locations for storing a unique sequence of random numbers. The scrambler forms another binary value by rearranging the bits of the input binary value as a function of the random number values in addition to altering the states of such bits as a function of the random number values and the numeric bit position values of sources of the input binary bits. The resulting binary value is applied to an alphanumeric encoder which converts the binary value into a series of alphanumeric characters containing a valid key value.

摘要翻译： 保护机制包括用于获取输入二进制值并产生唯一键值的装置，以及执行取得键值并产生输入二进制值的反向操作。 该机制包括扰码器，该加扰器包括具有多个多位容器位置的阵列，用于存储唯一的随机数序列。 加扰器通过将输入二进制值的位重新排列为随机数值的函数来形成另一个二进制值，除了改变作为随机数值的函数的这样的位的状态以及源的数字位位置值 输入二进制位。 所得到的二进制值被应用于将二进制值转换为包含有效键值的一系列字母数字字符的字母数字编码器。