公开(公告)号：US20080055963A1

公开(公告)日：2008-03-06

申请号：US11844512

申请日：2007-08-24

Applicant: Kwang-jin LEE ,  Woo-yeong CHO

Inventor： Kwang-jin LEE ,  Woo-yeong CHO

IPC: G11C11/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078

Abstract: In a phase change random access memory (PRAM) device, data is programmed in selected memory cells using a plurality of program loops. In each program loop, division program operations for cell groups including the selected memory cells are performed in consecutive timeslots.

Abstract translation: 在相变随机存取存储器（PRAM）装置中，使用多个程序循环将数据编程在所选存储单元中。 在每个程序循环中，在连续的时隙中执行包括所选存储单元的单元组的分割程序操作。

公开(公告)号：US07173082B2

公开(公告)日：2007-02-06

申请号：US10472593

申请日：2003-01-14

Applicant: Jeong-Heon Ahn ,  Chang-Sun Han ,  Yong-Hun Lee ,  Seon-Hee Han ,  Kwang-Jin Lee ,  Hyung-Jun Son

Inventor： Jeong-Heon Ahn ,  Chang-Sun Han ,  Yong-Hun Lee ,  Seon-Hee Han ,  Kwang-Jin Lee ,  Hyung-Jun Son

IPC: C08F285/00 ,  C08F265/06 ,  C08F2/16 ,  C08L51/04 ,  C08L27/06

CPC classification number: C08F285/00 ,  C08L27/06 ,  C08L51/003 ,  Y10S525/902 ,  C08F220/18 ,  C08L2666/24

Abstract: The invention relates to an acrylic impact modifier having a core-shell structure that provides an acrylic impact modifier composition comprising (a) a rubber core containing an alkyl acrylate polymer comprising at least two layers having different cross-linking densities, and (b) a shell containing an alkyl methacrylate polymer; to a process for the preparation of the acrylic impact modifier; and to a poly(vinyl chloride) composition comprising it. The acrylic impact modifier imparting excellent impact resistance was invented by employing multi-stage polymerization and at the same time by controlling the swelling index of rubber particles by changing the degree of cross-linking from stage to stage. And the poly(vinyl chloride) comprising the impact modifier of the present invention has good weatherability as well as excellent impact strength.

Abstract translation: 本发明涉及具有提供丙烯酸类抗冲改性剂组合物的核 - 壳结构的丙烯酸类抗冲击改性剂，其包含（a）含有至少两层具有不同交联密度的丙烯酸烷基酯聚合物的橡胶芯，和（b） 壳含有甲基丙烯酸烷基酯聚合物; 涉及制备丙烯酸类抗冲改性剂的方法; 和包含它的聚（氯乙烯）组合物。 通过采用多级聚合法，发明了赋予耐冲击性优异的丙烯酸类抗冲击改性剂，同时通过改变交联程度从阶段到控制橡胶粒子的溶胀指数。 并且包含本发明的抗冲改性剂的聚（氯乙烯）具有良好的耐候性以及优异的冲击强度。

公开(公告)号：US20060074148A1

公开(公告)日：2006-04-06

申请号：US10505517

申请日：2002-12-26

Applicant: Jeongheon Ahn ,  Seon-Hee Han ,  Kwang-Jin Lee

Inventor： Jeongheon Ahn ,  Seon-Hee Han ,  Kwang-Jin Lee

IPC: C09D151/00

CPC classification number: C08L55/02 ,  C08F257/02 ,  C08F265/04 ,  C08F265/06 ,  C08F265/08 ,  C08F285/00 ,  C08L27/06 ,  C08L51/003 ,  C08L51/04 ,  C08L67/02 ,  C08L69/00 ,  C08L2666/24 ,  C08L2666/02 ,  C08L2666/14 ,  C08L2666/04

Abstract: The present invention relates to an acrylic impact modifier having a multilayered structure, which offers both superior impact resistance and coloring characteristics to engineering plastics, such as polycarbonate (PC) and a polycarbonate/polybutylene terephthalate alloy resin, or to a polyvinyl chloride resin. The present invention provides an acrylic impact modifier having a multilayered structure comprising: a) a seed prepared by emulsion copolymerization of a vinylic monomer and a hydrophilic monomer; b) a rubbery core surrounding the seed and comprising a C2 to C8 alkyl acrylate polymer, and c) a shell surrounding the rubbery core and comprising a C1, to C4 alkyl methacrylate polymer, a method for preparing the same, and a thermoplastic resin comprising the same.

Abstract translation: 本发明涉及一种具有多层结构的丙烯酸类抗冲击改性剂，其对工程塑料如聚碳酸酯（PC）和聚碳酸酯/聚对苯二甲酸丁二醇酯合成树脂或聚氯乙烯树脂具有优异的抗冲击性和着色特性。 本发明提供具有多层结构的丙烯酸类抗冲改性剂，其包含：a）通过乙烯基单体和亲水单体的乳液共聚制备的种子; b）包围种子并包含C 2〜C 8烷基丙烯酸酯聚合物的橡胶状芯，和c）围绕橡胶核的壳，包含C 1 -C 6烷基， C 1至C 4烷基甲基丙烯酸酯聚合物，其制备方法和包含其的热塑性树脂。

公开(公告)号：US06947307B2

公开(公告)日：2005-09-20

申请号：US11030522

申请日：2005-01-06

Applicant: Yong-Dae Park ,  Kwang-Jin Lee

Inventor： Yong-Dae Park ,  Kwang-Jin Lee

IPC: G11C5/00 ,  G11C29/00 ,  G11C29/48 ,  G11C5/06

CPC classification number: G11C29/006 ,  G11C5/00 ,  G11C29/48

Abstract: A package map data outputting circuit of a semiconductor memory device embedded with a test circuit and a method for the same. In order to improve the reliability of package map data and easily output a greater amount of package map data, package map data is stored to package map data registers at the wafer level and then output through the test circuit at the package level.

Abstract translation: 嵌入测试电路的半导体存储器件的封装映射数据输出电路及其方法。 为了提高包地图数据的可靠性，并且容易地输出更大量的封装图数据，封装图数据被存储在晶片级的封装映射数据寄存器中，然后通过封装级的测试电路输出。

公开(公告)号：US20050117417A1

公开(公告)日：2005-06-02

申请号：US11030522

申请日：2005-01-06

Applicant: Yong-Dae Park ,  Kwang-Jin Lee

Inventor： Yong-Dae Park ,  Kwang-Jin Lee

IPC: G11C5/00 ,  G11C29/00 ,  G11C29/48 ,  G11C7/00

CPC classification number: G11C29/006 ,  G11C5/00 ,  G11C29/48

Abstract: The invention relates to a package map data outputting circuit of a semiconductor memory device embedded with a test circuit and a method for the same. In order to improve the reliability of package map data and easily output a greater amount of package map data, package map data is stored to package map data registers at the wafer level and then output through the test circuit at the package level.

Abstract translation: 本发明涉及嵌入有测试电路的半导体存储器件的封装图数据输出电路及其方法。 为了提高包地图数据的可靠性，并且容易地输出更大量的封装图数据，封装图数据被存储在晶片级的封装映射数据寄存器中，然后通过封装级的测试电路输出。

公开(公告)号：US06617894B2

公开(公告)日：2003-09-09

申请号：US10081359

申请日：2002-02-20

Applicant: Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

Inventor： Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

IPC: H03L700

CPC classification number: G06F1/10 ,  H03K5/135

Abstract: A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

公开(公告)号：US06594818B2

公开(公告)日：2003-07-15

申请号：US09814565

申请日：2001-03-21

Applicant: Su-Chul Kim ,  Hyun-Geun Byun ,  Kwang-Jin Lee ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Su-Chul Kim ,  Hyun-Geun Byun ,  Kwang-Jin Lee ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G06F1750

CPC classification number: H01L27/0207 ,  H01L21/82 ,  H01L27/10897

Abstract: A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different masks sets that form a different conductive pattern for each storage capacity or forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips

公开(公告)号：US06507224B1

公开(公告)日：2003-01-14

申请号：US10038171

申请日：2002-01-03

Applicant: Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

Inventor： Jong Cheol Lee ,  Yong Jin Yoon ,  Kwang Jin Lee

IPC: G11C2702

CPC classification number: H03K3/356139 ,  H03K3/012 ,  H03K3/356156

Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.

Abstract translation: 一种能够感测和放大具有非常小的摆动输入信号的外部信号的输入接收器。 输入接收机包括响应于时钟信号和延迟采样时钟信号的第一状态分别接收时钟信号和参考信号的时钟采样放大器，并且用于放大和采样外部信号与 分别响应于时钟的转变和延迟的采样时钟信号到第二状态的参考信号; 以及脉冲发生器，用于响应于延迟的采样时钟信号的第二状态和时钟采样放大器的输出，对电源电压进行预充电并选择性地拉低预充电信号以产生脉冲信号。

公开(公告)号：US06353575B2

公开(公告)日：2002-03-05

申请号：US09848785

申请日：2001-05-03

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: G11C818

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

Abstract: A semiconductor memory device for providing data together with an echo clock as an indicating signal representing a time for providing or presenting data in an electronic system is described. The device comprises an echo data latch circuit for generating a source signal of the echo clock in response to an output of a sense amplifier for sensing and amplifying the data of a memory cell during a read operation, and for producing the source signal of the echo clock in response to a predetermined level of power voltage during a write operation; and an output circuit, connected between the echo data latch circuit and an echo clock output terminal, for receiving the source signal of the echo clock and for outputting the echo clock to the output terminal in response to control data relating to an external clock, thereby minimizing or reducing clock skew and also preventing speed push.

Abstract translation: 描述了一种用于将数据与回波时钟一起提供的半导体存储器件，作为表示在电子系统中提供或呈现数据的时间的指示信号。 该装置包括回波数据锁存电路，用于响应读出放大器的输出产生回波时钟的源信号，用于在读取操作期间感测和放大存储器单元的数据，并且用于产生回波的源信号 在写入操作期间响应于预定电平电压的时钟; 以及连接在回波数据锁存电路和回波时钟输出端之间的输出电路，用于接收回波时钟的源信号，并响应于与外部时钟有关的控制数据将回波时钟输出到输出端，从而 最大限度地减少或减少时钟偏差，并防止速度推动。

公开(公告)号：US06307424B1

公开(公告)日：2001-10-23

申请号：US09656975

申请日：2000-09-07

Applicant: Kwang-Jin Lee

Inventor： Kwang-Jin Lee

IPC: H02J338

CPC classification number: H03K19/0005

Abstract: The invention relates to an impedance control output circuit of a semiconductor device and a method relevant thereto to prevent or minimize various problems caused by a transmission error by automatically resetting the impedance mismatch resulting from variances of supply voltage, temperature, other operational conditions. The impedance control output circuit of the semiconductor device comprises: an impedance detection, comparison and adjustment part for performing a normal operation and an automatic reset operation by comparing array reference voltage with pad voltage of a pad connected to an external resistance to obtain the pad voltage tracking the array reference voltage and by comparing the array reference voltage with the reference voltage predetermined by a resistant voltage divider for resetting the level of the array reference voltage to obtain the array reference voltage tracking the constant reference voltage; and a driving and data outputting part for driving impedance of a data output terminal of the semiconductor device in response to results of the normal and automatic reset operation to thereby output the internal data.

Abstract translation: 本发明涉及一种半导体器件的阻抗控制输出电路及其相关方法，以通过自动重置由电源电压，温度，其他操作条件的变化引起的阻抗失配来防止或最小化由传输误差引起的各种问题。 半导体器件的阻抗控制输出电路包括：通过将阵列参考电压与连接到外部电阻的焊盘的焊盘电压进行比较来执行正常操作和自动复位操作的阻抗检测，比较和调整部分，以获得焊盘电压 跟踪阵列参考电压，并通过将阵列参考电压与由电阻分压器预定的参考电压进行比较，以复位阵列参考电压的电平，以获得跟踪恒定参考电压的阵列参考电压; 以及驱动和数据输出部分，用于根据正常和自动复位操作的结果驱动半导体器件的数据输出端的阻抗，从而输出内部数据。