公开(公告)号：US20220209024A1

公开(公告)日：2022-06-30

申请号：US17556634

申请日：2021-12-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Arnaud YVON ,  Lionel JAOUEN

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761

Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a first doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.

公开(公告)号：US11373994B2

公开(公告)日：2022-06-28

申请号：US17028732

申请日：2020-09-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed Boufnichel

IPC: H01L27/02 ,  H01L21/762 ,  H01L29/06

Abstract: Methods and devices for protecting against electrical discharges are provided. One such device for protecting against electrical discharges includes a semiconductor substrate and an isolation trench in the semiconductor substrate. The isolation trench includes an enclosed space that contains a gas.

公开(公告)号：US20220068866A1

公开(公告)日：2022-03-03

申请号：US17458070

申请日：2021-08-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Christophe LEBRERE

IPC: H01L23/00 ,  H01L25/10

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

公开(公告)号：US11239376B2

公开(公告)日：2022-02-01

申请号：US16584774

申请日：2019-09-26

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Frederic Lanois

IPC: H01L29/10 ,  H01L29/861 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.

公开(公告)号：US20220020652A1

公开(公告)日：2022-01-20

申请号：US17491189

申请日：2021-09-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier ORY ,  Romain JAILLET

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L29/861

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

公开(公告)号：US20210336533A1

公开(公告)日：2021-10-28

申请号：US16858907

申请日：2020-04-27

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics LTD

Inventor： Ghafour BENABDELAZIZ ,  Laurent GONTHIER

IPC: H02M1/42 ,  H02M7/217 ,  H02M7/155

Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.

公开(公告)号：US11158556B2

公开(公告)日：2021-10-26

申请号：US16552464

申请日：2019-08-27

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory ,  Romain Jaillet

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L29/861

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

公开(公告)号：US20210296888A1

公开(公告)日：2021-09-23

申请号：US17197719

申请日：2021-03-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Eric COLLEONI

IPC: H02H9/04 ,  H02M1/088 ,  H02M1/32 ,  H02H3/087

Abstract: A device for discharging a capacitor includes a resistive component having a resistance value selectable from among at least three resistance values. The device is configured to be connected in parallel with the capacitor. A circuit operates to select the resistance value of the resistive component.

公开(公告)号：US20210184490A1

公开(公告)日：2021-06-17

申请号：US17118028

申请日：2020-12-10

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics, Inc.

Inventor： Mathieu ROUVIERE ,  Jeffrey BLAUSER, JR. ,  Karl GRANGE ,  Mohamed SAADNA

IPC: H02J7/34 ,  G06F1/26 ,  G06F13/42 ,  G06F1/3234

Abstract: A power supply interface includes a first switch that couples an input terminal to an output terminal. A voltage dividing bridge is coupled to receive a supply potential. A comparator has a first input connected to a first node of the bridge and a second input configured to receive a constant potential. A digital-to-analog converter generates a control voltage that is selectively coupled by a second switch to a second node of the bridge. A circuit control controls actuation of the second switch based on operating mode and generates a digital value input to the converter based on a negotiated set point of the supply potential applied to the input terminal.

公开(公告)号：US20210175204A1

公开(公告)日：2021-06-10

申请号：US17111198

申请日：2020-12-03

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic FALLOURD ,  Christophe SERRE

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.