公开(公告)号：US20130045576A1

公开(公告)日：2013-02-21

申请号：US13213092

申请日：2011-08-19

Applicant: Shih-Hung Tsai ,  Rai-Min Huang ,  Chien-Ting Lin

Inventor： Shih-Hung Tsai ,  Rai-Min Huang ,  Chien-Ting Lin

IPC: H01L21/336

CPC classification number: H01L29/7854

Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.

Abstract translation: 制造具有鳍结构的场效应晶体管的方法包括以下顺序。 首先，提供基板，并且在基板上形成至少一个翅片结构。 然后，执行蚀刻处理以使鳍结构中的至少一个上边缘圆弧。 最后，形成覆盖翅片结构的门。

公开(公告)号：US20120220113A1

公开(公告)日：2012-08-30

申请号：US13033616

申请日：2011-02-24

Applicant: Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966

Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

Abstract translation: 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽，然后在第一沟槽中形成第一金属层和第一材料层。 接下来，第一金属层和第一材料层变平。 去除第二牺牲栅极以形成第二沟槽，然后在第二沟槽中形成第二金属层和第二材料层。 最后，第二金属层和第二材料层变平。

公开(公告)号：US08141827B2

公开(公告)日：2012-03-27

申请号：US13175827

申请日：2011-07-02

Applicant: Chien-Ting Lin

Inventor： Chien-Ting Lin

IPC: F16M11/38

CPC classification number: F16M11/242

Abstract: Provided is a tripod structure of a stand, which is combined on a central post of the stand and allows the leg units of the stand to be folded, and includes: an upper tripod unit having a central post orifice and at least three leg unit connection parts evenly arranged at the outer periphery of the central post and formed with at least an accessory part, wherein the upper tripod unit is fastened at a preset location of the central post of the stand via the central post orifice, and each leg unit of the stand is respectively hinged with each leg unit connection part; and a lower tripod unit having a post plug and at least three moveable support rod connection parts evenly arranged at the outer periphery of the post plug, and each moveable support rod connection part is correspondingly formed with a leg unit buckling part and formed with at least an accessory part, wherein the post plug is installed at the distal end of the central post of the stand, and hinged to the leg unit and the moveable support rod connection part through a support rod, such that the leg units can be folded and respectively buckled with each corresponding leg unit buckling part.

Abstract translation: 提供了一种支架的三脚架结构，其组合在支架的中心柱上并且允许支架的腿单元折叠，并且包括：上三脚架单元，其具有中心柱孔和至少三个腿单元连接 部分均匀地布置在中心柱的外周并形成有至少一个附件部分，其中上三脚架单元经由中心柱孔紧固在支架的中心柱的预设位置处，并且每个支腿单元 支架分别与每个支腿单元连接部分铰接; 以及具有柱塞的下三脚架单元和在柱塞的外周均匀布置的至少三个可移动的支撑杆连接部分，并且每个可移动的支撑杆连接部分相应地形成有腿单元屈曲部分并至少形成 附件部分，其中柱塞安装在支架的中心柱的远端，并且通过支撑杆铰接到腿单元和可移动的支撑杆连接部分，使得腿单元可分别折叠 与每个相应的腿部屈曲部分扣合。

公开(公告)号：US20120064679A1

公开(公告)日：2012-03-15

申请号：US13304409

申请日：2011-11-25

Applicant: Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Cheng-Hsien Chou ,  Tian-Fu Chiang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/8238

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 首先，提供具有第一晶体管区域和第二晶体管区域的衬底。 接下来，在基板上形成层叠膜，其中层叠膜包括至少一个高k电介质层和第一金属层。 图案化层叠的膜以在第一晶体管区域和第二晶体管区域中形成多个栅极，在栅极上形成电介质层，并且介电层的一部分被平坦化，直到到达每个栅极的顶部。 第一金属层从第二晶体管区域的栅极去除，并且第二金属层形成在电介质层的表面上，每个栅极用于在第一晶体管区域和第二晶体管区域中形成多个金属栅极。

公开(公告)号：US07994576B2

公开(公告)日：2011-08-09

申请号：US12488592

申请日：2009-06-22

Applicant: Chih-Yu Tseng ,  Chien-Ting Lin ,  Kun-Szu Tseng ,  Cheng-Wen Fan ,  Victor-Chiang Liang

Inventor： Chih-Yu Tseng ,  Chien-Ting Lin ,  Kun-Szu Tseng ,  Cheng-Wen Fan ,  Victor-Chiang Liang

IPC: H01L27/01 ,  H01L27/12 ,  H01L23/62 ,  H01L31/0392 ,  H01L29/76

CPC classification number: H01L27/0629 ,  H01L21/84 ,  H01L28/20

Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管和电阻器的方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底中形成浅沟槽隔离; 在电阻区域的浅沟槽隔离中形成一个槽; 在所述晶体管区域中形成至少一个栅极和在所述电阻器区域的所述槽中形成电阻器; 并将栅极变换为金属栅极晶体管。

公开(公告)号：US07932146B2

公开(公告)日：2011-04-26

申请号：US12052728

申请日：2008-03-20

Applicant: Yi-Wen Chen ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Tian-Fu Chiang ,  Chien-Ting Lin ,  Guang-Hwa Ma

Inventor： Yi-Wen Chen ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Tian-Fu Chiang ,  Chien-Ting Lin ,  Guang-Hwa Ma

IPC: H01L21/8234 ,  H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/28079 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.

Abstract translation: 公开了一种用于制造金属栅极晶体管和多晶硅电阻器的方法。 首先，提供具有晶体管区域和电阻器区域的基板。 然后在衬底上形成多晶硅层以覆盖衬底的晶体管区域和电阻器区域。 接下来，去除设置在电阻器中的多晶硅层的一部分，并且对剩余的多晶硅层进行图案化以在布置在晶体管区域中的多晶硅层的表面和设置在电阻器中的多晶硅层的表面之间产生台阶高度 地区。

公开(公告)号：US20110018072A1

公开(公告)日：2011-01-27

申请号：US12894130

申请日：2010-09-29

Applicant: Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

Inventor： Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

IPC: H01L29/772

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S438/926

Abstract: A metal gate transistor is disclosed. The metal gate transistor preferably includes: a substrate, a metal gate disposed on the substrate, and a source/drain region disposed in the substrate with respect to two sides of the metal gate. The metal gate includes a U-shaped high-k dielectric layer, a U-shaped cap layer disposed over the surface of the U-shaped high-k dielectric layer, and a U-shaped metal layer disposed over the U-shaped cap layer.

Abstract translation: 公开了一种金属栅极晶体管。 金属栅极晶体管优选地包括：衬底，设置在衬底上的金属栅极和相对于金属栅极的两侧设置在衬底中的源极/漏极区域。 金属栅极包括U形高k电介质层，设置在U形高k电介质层表面上的U形盖层和设置在U形盖层上的U形金属层 。

公开(公告)号：US07838366B2

公开(公告)日：2010-11-23

申请号：US12101160

申请日：2008-04-11

Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

IPC: H01L21/8234

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

公开(公告)号：US07759202B2

公开(公告)日：2010-07-20

申请号：US12198111

申请日：2008-08-25

Applicant: Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

Inventor： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Yao-Tsung Huang ,  Guang-Hwa Ma

IPC: H01L21/8234 ,  H01L21/44

CPC classification number: H01L21/823842 ,  H01L21/823835 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/7843

Abstract: A semiconductor device includes a first gate structure including a gate dielectric layer directly contacting the substrate, a bottom electrode on the gate dielectric layer and a top electrode on the bottom electrode, and a second gate structure including a gate dielectric layer directly contacting the substrate and a gate electrode on the gate dielectric layer.

Abstract translation: 半导体器件包括：第一栅极结构，包括直接接触衬底的栅极电介质层，栅极电介质层上的底部电极和底部电极上的顶部电极;以及第二栅极结构，包括直接接触衬底的栅介质层和 栅电介质层上的栅电极。

公开(公告)号：US20100052074A1

公开(公告)日：2010-03-04

申请号：US12198128

申请日：2008-08-26

Applicant: Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

Inventor： Chien-Ting Lin ,  Li-Wei Cheng ,  Jung-Tsung Tseng ,  Che-Hua Hsu ,  Chih-Hao Yu ,  Tian-Fu Chiang ,  Yi-Wen Chen ,  Chien-Ming Lai ,  Cheng-Hsien Chou

IPC: H01L47/00 ,  H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S438/926

Abstract: A method for fabricating a transistor having metal gate is disclosed. First, a substrate is provided, in which the substrate includes a first transistor region and a second transistor region. A plurality of dummy gates is formed on the substrate, and a dielectric layer is deposited on the dummy gate. The dummy gates are removed to form a plurality of openings in the dielectric layer. A high-k dielectric layer is formed to cover the surface of the dielectric layer and the opening, and a cap layer is formed on the high-k dielectric layer thereafter. The cap layer disposed in the second transistor region is removed, and a metal layer is deposited on the cap layer of the first transistor region and the high-k dielectric layer of the second transistor region. A conductive layer is formed to fill the openings of the first transistor region and the second transistor region.

Abstract translation: 公开了一种用于制造具有金属栅极的晶体管的方法。 首先，提供衬底，其中衬底包括第一晶体管区域和第二晶体管区域。 在基板上形成多个虚拟栅极，在虚拟栅极上淀积介质层。 去除虚拟栅极以在电介质层中形成多个开口。 形成高k电介质层以覆盖电介质层和开口的表面，此后在高k电介质层上形成覆盖层。 去除设置在第二晶体管区域中的盖层，并且在第一晶体管区域的帽层和第二晶体管区域的高k电介质层上沉积金属层。 形成导电层以填充第一晶体管区域和第二晶体管区域的开口。