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公开(公告)号：US20190294416A1
公开(公告)日：2019-09-26
申请号：US15933081
申请日：2018-03-22
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Miao HU , John Paul Strachan
Abstract: According to examples, an apparatus may include an arithmetic logic unit (ALU) to apply a modification function to a digital input signal to generate a modified digital input signal, a digital-to-analog converter (DAC) to convert the modified digital input signal to an analog input signal, a crossbar array to apply an operation on the analog input signal to generate an analog output signal, and an analog-to-digital converter (ADC). The ADC may modify the analog output signal to compensate for application of the modification function to the digital input signal, may convert the modified analog output signal to a digital output signal, and may output the digital output signal.
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公开(公告)号：US10424378B2
公开(公告)日：2019-09-24
申请号：US16073922
申请日：2016-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.
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公开(公告)号：US10410716B2
公开(公告)日：2019-09-10
申请号：US15570980
申请日：2015-09-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Miao Hu , Zhiyong Li , John Paul Strachan
Abstract: A crossbar array, comprises a plurality of row lines, a plurality of column lines intersecting the plurality of row lines at a plurality of intersections, a plurality of junctions coupled between the plurality of row lines and the plurality of column lines at a portion of the plurality of intersections, and a plurality of diagonal control lines coupled to the plurality of junctions. Each junction comprises a resistive memory element and a transistor, and the junctions are positioned to calculate a matrix multiplication of a first matrix and a second matrix.
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公开(公告)号：US20190236111A1
公开(公告)日：2019-08-01
申请号：US16063793
申请日：2016-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Benjamin Feinberg , John Paul Strachan
CPC classification number: G06F17/16 , G06G7/16 , G11C7/16 , G11C13/0002 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0069
Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.
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公开(公告)号：US20190027217A1
公开(公告)日：2019-01-24
申请号：US16065771
申请日：2016-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
Abstract: In one example in accordance with the present disclosure a memristive array is described. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.
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Patent Agency Ranking
公开(公告)号：US20180373674A1
公开(公告)日：2018-12-27
申请号：US16052507
申请日：2018-08-01
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Miao Hu , John Paul Strachan , Naveen Muralimanohar
Abstract: Examples herein relate to convolution accelerators. An example convolution accelerator may include a transformation crossbar array programmed to calculate a Fourier Transformation of a first vector with a transformation matrix and a Fourier Transformation of a second vector with the transformation matrix. A circuit of the example convolution accelerator may multiply the Fourier Transformation of the first vector with the Fourier Transformation of the second vector to calculate a product vector. The example convolution accelerator may have an inverse transformation crossbar array programmed to calculate an Inverse Fourier Transformation of the product vector according to an inverse transformation matrix.
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公开(公告)号：US20180253643A1
公开(公告)日：2018-09-06
申请号：US15449071
申请日：2017-03-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Miao Hu , John Paul Strachan
CPC classification number: G06N3/0635 , G06F7/5443 , G06F2207/4802 , G06F2207/4824 , G11C13/0069 , H03M1/1245
Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.
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公开(公告)号：US20180218771A1
公开(公告)日：2018-08-02
申请号：US15418040
申请日：2017-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
CPC classification number: G11C13/0069 , G06F17/16
Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.
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公开(公告)号：US20180121416A1
公开(公告)日：2018-05-03
申请号：US15336907
申请日：2016-10-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G06F17/27
CPC classification number: G06F17/2735
Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.
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公开(公告)号：US20180108403A1
公开(公告)日：2018-04-19
申请号：US15556361
申请日：2015-04-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning Ge , Jianhua Yang , Miao Hu , John Paul Strachan
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0007 , G11C13/0033 , G11C13/0038 , G11C13/0069
Abstract: A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compensation circuit to determine a compensation voltage based on the electrical control signal and pre-calibrated temperature data of the memristor crossbar array.
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