公开(公告)号：US20190311759A1

公开(公告)日：2019-10-10

申请号：US16387227

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22 ,  G06F13/40

Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

公开(公告)号：US10395715B2

公开(公告)日：2019-08-27

申请号：US15687019

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22

Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

公开(公告)号：US10304514B2

公开(公告)日：2019-05-28

申请号：US15641783

申请日：2017-07-05

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22 ,  G06F13/40

Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

公开(公告)号：US20160254049A1

公开(公告)日：2016-09-01

申请号：US15152449

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

公开(公告)号：US09087578B2

公开(公告)日：2015-07-21

申请号：US14041585

申请日：2013-09-30

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C13/00 ,  G11C7/14

CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/04 ,  G11C7/14 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector.

Abstract translation: 本公开涉及生成用于存储器件的参考电流。 在一个方面，诸如相变存储器件的非易失性存储器件可以至少部分地基于参考电流来确定存储在非易失性存储器单元中的诸如位之类的数据位的值。 参考电流可以通过在由电压偏置偏置的节点处的电流进行镜像来产生。 可配置的电阻电路可以具有可配置的电阻。 可配置电阻电路的电阻可以串联在节点和电阻性非易失性存储器元件之间。 在一些实施例中，多个非易失性存储器元件可以各自在可配置电阻电路的电阻和相应的选择器之间串联电连接。

公开(公告)号：US20140241049A1

公开(公告)日：2014-08-28

申请号：US13775868

申请日：2013-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C7/12 ,  G11C5/14 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract translation: 描述用于补偿存储器中的字线上的电压增加的装置，感测电路和方法。 示例性设备包括位线，耦合到位线的存储器单元，耦合到存储单元的双极选择器器件，耦合到双极选择器器件的字线和耦合到字线的字线驱动器。 该装置还包括：模型字线电路，被配置为模拟字线的阻抗和字线驱动器的阻抗，以及耦合到位线和模型字线电路的感测电路。 感测电路被配置为基于单元电流感测存储器单元的状态，并提供指示存储单元的状态的感测信号。 感测电路还被配置为响应于由模型字线电路建模的字线电压的增加来调整位线电压。