公开(公告)号：US20210241822A1

公开(公告)日：2021-08-05

申请号：US16973241

申请日：2019-05-25

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C11/406

Abstract: An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.

公开(公告)号：US20210098033A1

公开(公告)日：2021-04-01

申请号：US17065278

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US10885946B2

公开(公告)日：2021-01-05

申请号：US16801990

申请日：2020-02-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065 ,  G11C5/02

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US20200351463A1

公开(公告)日：2020-11-05

申请号：US16859243

申请日：2020-04-27

Applicant: Rambus Inc.

Inventor： Jay Endsley ,  Thomas Vogelsang ,  Craig M. Smith ,  Michael Guidash ,  Alexander C. Schneider

IPC: H04N5/378 ,  H04N5/235 ,  H04N5/353 ,  H04N5/355

Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.

公开(公告)号：US20200265873A1

公开(公告)日：2020-08-20

申请号：US16801990

申请日：2020-02-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  G11C5/02 ,  H01L25/065 ,  H01L27/108 ,  H01L23/48

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US20200066314A1

公开(公告)日：2020-02-27

申请号：US16528523

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/08 ,  G11C7/22 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4076 ,  G11C5/02 ,  G11C7/08

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20190237130A1

公开(公告)日：2019-08-01

申请号：US16261937

申请日：2019-01-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C11/4093 ,  G11C11/4097 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20190166321A1

公开(公告)日：2019-05-30

申请号：US16197270

申请日：2018-11-20

Applicant: Rambus Inc.

Inventor： John Ladd ,  Michael Guidash ,  Craig M. Smith ,  Thomas Vogelsang ,  Jay Endsley ,  Michael T. Ching ,  James E. Harris

IPC: H04N5/365 ,  H04N5/369 ,  H04N5/357 ,  H04N5/378 ,  H04N5/3745 ,  H04N5/355

Abstract: A sequence of control voltage levels are applied to a control signal line capacitively coupled to a floating diffusion node of a pixel to sequentially adjust a voltage level of the floating diffusion node. A pixel output signal representative of the voltage level of the floating diffusion node is compared with a reference voltage to identify a first control voltage level of the sequence of control voltage levels for which the voltage level of the floating diffusion node exceeds the reference voltage.

公开(公告)号：US10277843B2

公开(公告)日：2019-04-30

申请号：US15589149

申请日：2017-05-08

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Michael Guidash ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris

IPC: H04N3/14 ,  H04N5/335 ,  H04N5/355 ,  H04N5/378 ,  H04N5/347 ,  H04N5/3745 ,  H01L27/146 ,  H04N5/374 ,  H01L31/113

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

公开(公告)号：US10274652B2

公开(公告)日：2019-04-30

申请号：US15423892

申请日：2017-02-03

Applicant: Rambus Inc.

Inventor： Jay Endsley ,  Thomas Vogelsang

IPC: H04N5/225 ,  G02B5/18 ,  H04N5/335

Abstract: An imaging device uses a grating to produce an interference pattern for capture by a photodetector array. Digital photographs and other image information can then be extracted from the pattern. An integrated processor locally supports this extraction by upsampling the captured interference pattern and deconvolving the upsampled pattern with an image-calculation parameter set that represents the grating at a resolution greater than that provided by the photodetector array. Deconvolving the upsampled pattern with a high-resolution parameter increases the resolution of extracted image information.