公开(公告)号：US06822259B1

公开(公告)日：2004-11-23

申请号：US10126193

申请日：2002-04-19

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： H01L2358

CPC分类号： H01L21/28273 ,  G11C16/04 ,  G11C29/006 ,  G11C2029/0403 ,  G11C2029/5002

摘要： A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.

摘要翻译： 一种用于测试包括堆叠浮栅结构的半导体的方法和装置。 浮动门被编程（710）。 电应力或干扰电压在特定条件（720）中用源极和漏极施加到控制栅极。 在应力之后，测量漏极电流与栅极电压的关系（730）。 编程，应力和测量的顺序可以重复（740），具有不同的源和漏源条件。 更具体地，在将源极保持在地面的同时将漏极保持在接地处时，将正和负偏压施加到源极，并且在将源保持在地面的同时将类似的偏压施加到漏极。 通过检查在该应力应用序列之后采取的测量信息，可以将源极边缘或漏极边缘的叠栅极边缘缺陷识别（750）。 以这种新颖的方式，可以通过非破坏性手段识别和定位堆叠栅极边缘缺陷，并且可以采取对半导体制造工艺和/或部分制造的晶片的校正动作。

公开(公告)号：US06797650B1

公开(公告)日：2004-09-28

申请号：US10342032

申请日：2003-01-14

申请人： Zhigang Wang ,  Nian Yang ,  John Jianshi Wang ,  Jiang Li

发明人： Zhigang Wang ,  Nian Yang ,  John Jianshi Wang ,  Jiang Li

IPC分类号： H01L2131

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/513 ,  H01L29/518

摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.

摘要翻译： 本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。 化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。 基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。 本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。 本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

公开(公告)号：US06751146B1

公开(公告)日：2004-06-15

申请号：US10338333

申请日：2003-01-07

申请人： Zhigang Wang ,  Jianshi Wang ,  Imran Khan

发明人： Zhigang Wang ,  Jianshi Wang ,  Imran Khan

IPC分类号： G11C700

CPC分类号： G11C16/3431 ,  G11C11/406 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/3418

摘要： A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.

摘要翻译： 一种包括用于电荷恢复的逻辑的非易失性存储器件。 恢复逻辑控制用于确定与从存储单元阵列选择的存储单元的阈值电压相关联的值的读取电路，并将该值与一个或多个边界值进行比较，以确定存储器单元值是否超出界限 。 在存储单元值超出范围的情况下，建立存储单元的目标值。 恢复逻辑控制将写入脉冲施加到存储器单元的写入电路。 必要时重复读取和写入过程，直到达到存储单元的目标值。 恢复逻辑可以包括用于对存储器单元阵列执行统计分析以便确定目标恢复值的处理器。 阵列内的存储单元可能被保留供恢复逻辑使用。

公开(公告)号：US06677442B1

公开(公告)日：2004-01-13

申请号：US09698286

申请日：2000-10-30

申请人： Zhigang Wang ,  Wensheng Winston Lin ,  Hua Xin ,  Xiaohua Wu

发明人： Zhigang Wang ,  Wensheng Winston Lin ,  Hua Xin ,  Xiaohua Wu

IPC分类号： C12N1552

CPC分类号： C12N9/1241

摘要： The present invention relates to a human cDNA homologous to the yeast REV1 gene. The sequence of human REV1 (hREV1) gene is described.

摘要翻译： 本发明涉及与酵母REV1基因同源的人cDNA。 描述人REV1（hREV1）基因的序列。

公开(公告)号：US06646462B1

公开(公告)日：2003-11-11

申请号：US10178144

申请日：2002-06-24

申请人： Nian Yang ,  Zhigang Wang ,  Xin Guo

发明人： Nian Yang ,  Zhigang Wang ,  Xin Guo

IPC分类号： H01L2998

CPC分类号： H01L22/34 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated. The source/drain junction overlap length is then used to calculate the channel length of the small device.

摘要翻译： 本发明一般涉及一种确定诸如MOS晶体管的小器件的源/漏结重叠和沟道长度的方法。 提供具有已知通道长度的大参考装置，并且其上形成有装置的源极，漏极和基板接地。 将预定的栅极电压施加到大型器件的栅极，并测量参考器件的栅极到沟道电流。 形成小型器件的源极，漏极和衬底接地，并且将预定电压施加到小器件的栅极，并且测量小器件的栅极到沟道电流。 衬底和小器件的源极或漏极中的一个浮置，并且将预定的漏极电压施加到不浮动的源极或漏极。 测量用于小器件的漏极电流的栅极，并计算源极/漏极结重叠长度。 然后使用源极/漏极结重叠长度来计算小器件的沟道长度。

公开(公告)号：US06570787B1

公开(公告)日：2003-05-27

申请号：US10126330

申请日：2002-04-19

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.

摘要翻译： 本发明涉及一种闪存阵列架构，其包括以NOR型阵列配置布置的多个闪存单元。 多个闪存单元中的每一个具有耦合在一起以形成公共源的源极端子。 阵列结构还包括耦合在阵列的公共源和预定电位之间的公共源选择部件。 公共源选择组件可操作以将公共源耦合到处于第一状态的预定电位，并且在第二状态下将公共源与预定电位电隔离或浮动，从而减少与激活位相关联的未选择单元的泄漏 在程序运行模式下运行。

公开(公告)号：US06472236B1

公开(公告)日：2002-10-29

申请号：US09904740

申请日：2001-07-13

申请人： Zhigang Wang ,  Nian Yang ,  Tien-Chun Yang

发明人： Zhigang Wang ,  Nian Yang ,  Tien-Chun Yang

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks. A respective total effective oxide thickness, EOTMOS, is measured for each of the first plurality of test MOS stacks. A first graph having total effective oxide thickness as a first axis and having deposition time for forming the first dielectric structure as a second axis is generated by plotting the respective total effective oxide thickness, EOTMOS, versus the respective deposition time for forming the respective first dielectric structure for each of the first plurality of test MOS stacks. The respective second effective oxide thickness of the respective second dielectric structure that is substantially same for each of the first plurality of test MOS stacks is determined from an intercept of the first axis of total effective oxide thickness when deposition time for forming the first dielectric structure of the second axis is substantially zero in the first graph.

摘要翻译： 用于确定形成MOS（金属氧化物半导体）堆叠的第一和第二电介质结构中的每一个的相应有效氧化物厚度的系统和方法。 形成第一多个测试MOS（金属氧化物半导体）堆叠，并且每个测试MOS堆叠包括由第一电介质材料和由第二电介质材料组成的相应的第二电介质结构的相应的第一电介质结构。 形成对应于第一多个测试MOS堆叠中的每一个的相应的第一介电结构的各自的沉积时间被改变，使得相应的第一介电结构的相应的第一有效氧化物厚度对于第一多个测试MOS堆叠而言是变化的。 相应的第二介电结构的相应的第二有效氧化物厚度被保持为对于第一多个测试MOS堆叠中的每一个基本相同。 对于第一多个测试MOS堆叠中的每一个测量相应的总有效氧化物厚度EOTMOS。 通过绘制相应的总有效氧化物厚度EOTMOS，相对于形成相应的第一电介质的相应沉积时间，产生具有总有效氧化物厚度作为第一轴并具有用于形成第一电介质结构作为第二轴的沉积时间的第一图 所述第一多个测试MOS堆叠中的每一个的结构。 对于第一多个测试MOS堆叠中的每一个基本上相同的相应的第二介电结构的相应的第二有效氧化物厚度是从形成第一介电结构的沉积时间的总有效氧化物厚度的第一轴的截距来确定的 在第一图中第二轴基本为零。