公开(公告)号：US06606273B1

公开(公告)日：2003-08-12

申请号：US10121140

申请日：2002-04-11

申请人： Xin Guo ,  Nian Yang ,  Zhigang Wang

发明人： Xin Guo ,  Nian Yang ,  Zhigang Wang

IPC分类号： G11C700

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/006 ,  G11C29/50

摘要： Methods are disclosed for determining tunnel oxide reliability of flash memory devices in a wafer prior to sorting and packaging without damaging or stressing the devices. The methods comprise measuring an initial threshold voltage of a test cell having the same tunnel oxide as other flash cells on the wafer, applying an erase stress to the test cell for a first time period and a program stress to the test cell for a second time period, and measuring the final threshold voltage of the test cell. The difference between the initial and final threshold voltages is then used to determine or estimate the tunnel oxide reliability of the flash memory cells on the wafer.

摘要翻译： 公开了用于在分选和包装之前确定晶片中闪存器件的隧道氧化物可靠性的方法，而不会损坏或强调器件。 该方法包括测量具有与晶片上的其它闪存单元相同的隧道氧化物的测试单元的初始阈值电压，将第一时间段的擦除应力施加到测试单元上，并且向测试单元施加程序应力第二次 周期，并测量测试单元的最终阈值电压。 然后使用初始阈值电压和最终阈值电压之间的差异来确定或估计晶片上闪存单元的隧道氧化物可靠性。

公开(公告)号：US06864106B1

公开(公告)日：2005-03-08

申请号：US10217965

申请日：2002-08-12

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： G01R31/26 ,  G11C29/50 ,  H01L21/66 ,  G01R27/28

CPC分类号： G11C29/50 ,  G01R31/2621 ,  G11C16/04 ,  G11C2029/5002

摘要： A method for detecting tunnel oxide encroachment on a memory device. In one method embodiment, the present invention applies a baseline voltage burst to a gate of the memory device. Next, the present embodiment generates a baseline performance distribution graph of bit line current as a function of gate voltage for the memory device. The present embodiment then applies a channel program voltage burst to the gate of the memory device. Moreover, the present embodiment generates a channel program performance distribution graph of bit line current as a function of gate voltage for the memory device. The present embodiment then applies a channel erase voltage burst to the gate of the memory device. Additionally, the present embodiment generates a channel erase performance distribution graph of bit line current as a function of gate voltage for the memory device. A comparison of the channel program performance distribution graph and the channel erase performance distribution graph with respect to said baseline performance distribution graph is then performed. In so doing, an asymmetric distribution of the channel program performance distribution graph and the channel erase performance distribution graph with respect to the baseline performance distribution indicates tunnel oxide encroachment.

摘要翻译： 一种用于检测存储器件上的隧道氧化物侵蚀的方法。 在一个方法实施例中，本发明将基线电压脉冲串应用于存储器件的栅极。 接下来，本实施例生成作为存储器件的栅极电压的函数的位线电流的基线性能分布图。 本实施例然后将通道编程电压脉冲串施加到存储器件的栅极。 此外，本实施例产生作为存储器件的栅极电压的函数的位线电流的通道程序性能分布图。 本实施例然后将通道擦除电压脉冲串施加到存储器件的栅极。 此外，本实施例产生作为存储器件的栅极电压的函数的位线电流的沟道擦除性能分布图。 然后执行频道节目性能分布图与信道擦除性能分布图相对于所述基线性能分布图的比较。 在这样做时，相对于基线性能分布，信道节目性能分布图和信道擦除性能分布图的不对称分布表示隧道氧化物侵蚀。

公开(公告)号：US06991987B1

公开(公告)日：2006-01-31

申请号：US10306382

申请日：2002-11-27

申请人： Xin Guo ,  Nian Yang ,  Zhigang Wang

发明人： Xin Guo ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  C23C16/0218 ,  C23C16/0227 ,  C23C16/308 ,  H01L21/3144

摘要： A process technology effectuates production of low defect homogeneous oxynitride, which can be applied in tunneling dielectrics with high dielectric constants and low barrier heights for flash memory devices, and as gate oxide for ultra-thin logic devices. The process technology involves varying the oxygen content in a the homogeneous oxynitride film comprising a part of the flash memory device, which effectively increases the dielectric constant of the oxynitride film and lowers its barrier height. In one such process, a controlled co-flow of N2O is introduced into a CVD deposition process. This process effectuates production of a oxynitride film with uniform distributions of nitrogen and oxygen throughout.

摘要翻译： 一种工艺技术可以实现低缺陷均匀氮氧化物的生产，其可以应用于具有高介电常数的隧道电介质和用于闪存器件的低屏障高度，以及用作超薄逻辑器件的栅极氧化物。 该工艺技术涉及改变包括闪存器件的一部分的均匀氮氧化物膜中的氧含量，其有效地增加氧氮化物膜的介电常数并降低其势垒高度。 在一种这样的方法中，将N 2 O 2的受控共流引入到CVD沉积工艺中。 该方法实现了氮气和氧气的均匀分布的氮氧化物膜的生产。

公开(公告)号：US06828623B1

公开(公告)日：2004-12-07

申请号：US10232487

申请日：2002-08-30

申请人： Xin Guo ,  Nian Yang ,  Zhigang Wang

发明人： Xin Guo ,  Nian Yang ,  Zhigang Wang

IPC分类号： H01L29788

CPC分类号： H01L29/518 ,  H01L21/28273 ,  H01L29/7885

摘要： A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including homogeneous oxynitride. The tunnel oxide dielectric layer separates a floating gate from a channel region that is formed between a source region and a drain region in a substrate. The flash memory cell further includes a dielectric layer that separates a control gate from the floating gate. In one case, the homogenous oxynitride is a defect free silicon nitride. The homogeneity of the oxynitride is due to the uniform distribution of nitride within the tunnel oxide dielectric layer. Further, the use of the homogeneous oxynitride can increase the dielectric constant and lower the barrier height of the tunnel oxide dielectric layer for increased performance. Also, the homogenous oxynitride supports source-side channel hot hole erasing in the flash memory cell.

摘要翻译： 具有均匀氧氮化物隧道电介质的存储器件。 具体地，本发明描述了一种闪存单元，其包括包括均匀氮氧化物的隧道氧化物介电层。 隧道氧化物电介质层将浮置栅极与形成在衬底中的源极区域和漏极区域之间的沟道区域分离。 闪存单元还包括将控制栅极与浮动栅极分离的介质层。 在一种情况下，均匀的氮氧化合物是无缺陷的氮化硅。 氧氮化物的均匀性是由于氮化物在隧​​道氧化物介电层内的均匀分布。 此外，为了提高性能，使用均匀的氮氧化物可以增加介电常数并降低隧道氧化物介电层的势垒高度。 此外，均匀的氮氧化物支持闪存单元中的源极侧通道热孔擦除。

公开(公告)号：US06822259B1

公开(公告)日：2004-11-23

申请号：US10126193

申请日：2002-04-19

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： H01L2358

CPC分类号： H01L21/28273 ,  G11C16/04 ,  G11C29/006 ,  G11C2029/0403 ,  G11C2029/5002

摘要： A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.

摘要翻译： 一种用于测试包括堆叠浮栅结构的半导体的方法和装置。 浮动门被编程（710）。 电应力或干扰电压在特定条件（720）中用源极和漏极施加到控制栅极。 在应力之后，测量漏极电流与栅极电压的关系（730）。 编程，应力和测量的顺序可以重复（740），具有不同的源和漏源条件。 更具体地，在将源极保持在地面的同时将漏极保持在接地处时，将正和负偏压施加到源极，并且在将源保持在地面的同时将类似的偏压施加到漏极。 通过检查在该应力应用序列之后采取的测量信息，可以将源极边缘或漏极边缘的叠栅极边缘缺陷识别（750）。 以这种新颖的方式，可以通过非破坏性手段识别和定位堆叠栅极边缘缺陷，并且可以采取对半导体制造工艺和/或部分制造的晶片的校正动作。

公开(公告)号：US06646462B1

公开(公告)日：2003-11-11

申请号：US10178144

申请日：2002-06-24

申请人： Nian Yang ,  Zhigang Wang ,  Xin Guo

发明人： Nian Yang ,  Zhigang Wang ,  Xin Guo

IPC分类号： H01L2998

CPC分类号： H01L22/34 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention generally relates to a method of determining a source/drain junction overlap and a channel length of a small device, such as a MOS transistor. A large reference device having a known channel length is provided, and a source, drain, and substrate on which the device has been formed are grounded. A predetermined gate voltage is applied to a gate of the large device, and a gate to channel current of the reference device is measured. A source, drain, and substrate on which the small device has been formed are grounded, and the predetermined voltage is applied to a gate of the small device, and a gate to channel current of the small device is measured. The substrate and one of the source or the drain of the small device is floated, and a predetermined drain voltage is applied to source or the drain which is not floating. A gate to drain current for the small device is measured, and a source/drain junction overlap length is calculated. The source/drain junction overlap length is then used to calculate the channel length of the small device.

摘要翻译： 本发明一般涉及一种确定诸如MOS晶体管的小器件的源/漏结重叠和沟道长度的方法。 提供具有已知通道长度的大参考装置，并且其上形成有装置的源极，漏极和基板接地。 将预定的栅极电压施加到大型器件的栅极，并测量参考器件的栅极到沟道电流。 形成小型器件的源极，漏极和衬底接地，并且将预定电压施加到小器件的栅极，并且测量小器件的栅极到沟道电流。 衬底和小器件的源极或漏极中的一个浮置，并且将预定的漏极电压施加到不浮动的源极或漏极。 测量用于小器件的漏极电流的栅极，并计算源极/漏极结重叠长度。 然后使用源极/漏极结重叠长度来计算小器件的沟道长度。

公开(公告)号：US06570787B1

公开(公告)日：2003-05-27

申请号：US10126330

申请日：2002-04-19

申请人： Zhigang Wang ,  Nian Yang ,  Xin Guo

发明人： Zhigang Wang ,  Nian Yang ,  Xin Guo

IPC分类号： G11C1604

CPC分类号： G11C16/12

摘要： The present invention relates to a flash memory array architecture comprising a plurality of flash memory cells arranged in a NOR type array configuration. Each of the plurality of flash memory cells have a source terminal coupled together to form a common source. The array architecture further comprises a common source selection component coupled between the common source of the array and a predetermined potential. The common source selection component is operable to couple the common source to the predetermined potential in a first state and electrically isolate or float the common source from the predetermined potential in a second state, thereby reducing leakage of non-selected cells associated with the activated bit line during a program mode of operation.

摘要翻译： 本发明涉及一种闪存阵列架构，其包括以NOR型阵列配置布置的多个闪存单元。 多个闪存单元中的每一个具有耦合在一起以形成公共源的源极端子。 阵列结构还包括耦合在阵列的公共源和预定电位之间的公共源选择部件。 公共源选择组件可操作以将公共源耦合到处于第一状态的预定电位，并且在第二状态下将公共源与预定电位电隔离或浮动，从而减少与激活位相关联的未选择单元的泄漏 在程序运行模式下运行。

公开(公告)号：US06825083B1

公开(公告)日：2004-11-30

申请号：US10126814

申请日：2002-04-19

申请人： Nian Yang ,  John Jianshi Wang ,  Xin Guo ,  Tien-Chun Yang

发明人： Nian Yang ,  John Jianshi Wang ,  Xin Guo ,  Tien-Chun Yang

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.

摘要翻译： 一种半导体集成电路制造方法。 具体地，本发明的一个实施例公开了一种用于减少硅的浅沟槽隔离（STI）角凹槽的方法，以便在包括闪存器件380的集成电路400中减少外围薄栅晶体管器件480的STI边缘变薄，以及两者 厚390和薄型480栅极晶体管器件。 该方法开始于在半导体衬底430上形成隧道氧化物层310以形成闪存器件380（步骤220）。 掩模350形成在薄栅极晶体管器件480上，以阻止形成厚栅极氧化物层360以形成厚栅极晶体管器件390（步骤230）。 掩模350通过在形成用于薄栅极晶体管器件480的薄氧化物层410之前消除厚栅极氧化层360的去除来减少浅沟槽隔离（STI）凹陷。

公开(公告)号：US07020022B1

公开(公告)日：2006-03-28

申请号：US10887782

申请日：2004-07-09

申请人： John Wang ,  Zhigang Wang ,  Xin Guo

发明人： John Wang ,  Zhigang Wang ,  Xin Guo

IPC分类号： G11C16/00

CPC分类号： G11C16/28

摘要： A method for standard reference cell design is herein disclosed. The method includes determining a first number of individual bits to be employed in a standard reference cell design based on the number of individual bits that are included in core memory cells that are to be measured using the standard reference cell. The method further includes determining a range of variation in the core memory cells to be measured that is due to process variation in the generation of the core memory cells. In addition, the method includes determining an additional number of individual bits to be included in the standard reference cell design based on the determined range of variation. A standard reference cell that includes a number of individual bits equal to the sum of both the first and the additional number of individual bits is generated.

摘要翻译： 本文公开了一种用于标准参考电池设计的方法。 该方法包括基于使用标准参考小区来测量的核心存储器单元中包含的各个比特的数量来确定在标准参考小区设计中采用的单个比特的第一数量。 该方法还包括确定由于核心存储器单元的产生中的过程变化而导致的要测量的核心存储器单元的变化范围。 此外，该方法包括基于所确定的变化范围来确定要包括在标准参考单元设计中的附加数量的单独位。 生成包括等于第一个和另外个数的个数之和的个别位数的标准参考单元。

公开(公告)号：US06617639B1

公开(公告)日：2003-09-09

申请号：US10176594

申请日：2002-06-21

申请人： Zhigang Wang ,  Xin Guo ,  Yue-Song He

发明人： Zhigang Wang ,  Xin Guo ,  Yue-Song He

IPC分类号： H01L29788

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883

摘要： A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.

摘要翻译： 一种浮栅闪存器件，包括：衬底，包括源极区，漏极区和位于其间的沟道区; 位于通道区域上方并通过隧道介电材料层与沟道区分离的浮栅电极; 以及控制栅电极，其位于所述浮置栅电极的上方，并且通过间隔电介质层与所述浮栅电极分离，所述互聚电介质层包括具有与所述浮栅电极相邻的底电介质材料层的修饰的ONO结构，顶介电材料 层，以及包括氮化物并位于底部电介质材料层和顶部电介质材料层之间的中心层，其中隧道电介质材料层和底部电介质材料层和底部电介质材料层中的至少一个 顶部介电材料层，包括高K电介质材料。