公开(公告)号：US20230132375A9

公开(公告)日：2023-04-27

申请号：US17123413

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US11355597B2

公开(公告)日：2022-06-07

申请号：US17153976

申请日：2021-01-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Tomomatsu ,  Sameer Pendharkar ,  Hiroshi Yamasaki

IPC: H01L23/48 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423 ,  H01L23/482 ,  H01L29/20

Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

公开(公告)号：US11189721B2

公开(公告)日：2021-11-30

申请号：US16995133

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L29/51

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US11004971B2

公开(公告)日：2021-05-11

申请号：US16264848

申请日：2019-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Ming-yeh Chuang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.

公开(公告)号：US10957774B2

公开(公告)日：2021-03-23

申请号：US16127281

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/10

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US10861943B2

公开(公告)日：2020-12-08

申请号：US16216874

申请日：2018-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.

公开(公告)号：US10714474B2

公开(公告)日：2020-07-14

申请号：US15636055

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/761 ,  H01L29/06 ,  H01L27/088 ,  H01L29/49

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US20200168733A1

公开(公告)日：2020-05-28

申请号：US16776544

申请日：2020-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/761 ,  H01L29/10 ,  H03K17/687 ,  H01L21/28 ,  H03K17/12 ,  H01L29/08 ,  H01L27/07

Abstract: A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.

公开(公告)号：US10651274B2

公开(公告)日：2020-05-12

申请号：US15876989

申请日：2018-01-22

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

公开(公告)号：US20200064394A1

公开(公告)日：2020-02-27

申请号：US16400336

申请日：2019-05-01

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: G01R31/26 ,  G01R27/26

Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.