公开(公告)号：US11769824B2

公开(公告)日：2023-09-26

申请号：US17165697

申请日：2021-02-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/0891 ,  H01L29/42316

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US10134596B1

公开(公告)日：2018-11-20

申请号：US15820168

申请日：2017-11-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L21/02

Abstract: In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.

公开(公告)号：US09412668B2

公开(公告)日：2016-08-09

申请号：US14712148

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US20130105909A1

公开(公告)日：2013-05-02

申请号：US13663015

申请日：2012-10-29

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US12166119B2

公开(公告)日：2024-12-10

申请号：US18357431

申请日：2023-07-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US10312095B1

公开(公告)日：2019-06-04

申请号：US16163602

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

公开(公告)号：US09431302B2

公开(公告)日：2016-08-30

申请号：US14712133

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

公开(公告)号：US09184163B1

公开(公告)日：2015-11-10

申请号：US14803678

申请日：2015-07-20

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Sameer Pendharkar

IPC: H01L27/092 ,  H01L29/36 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

公开(公告)号：US20140252485A1

公开(公告)日：2014-09-11

申请号：US13789477

申请日：2013-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Amitava Chatterjee

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/105 ,  H01L29/42364

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract translation: 第一类型的杂质原子通过栅极和薄栅极电介质注入到在沟道区的中间点处基本上仅具有第一类型的杂质原子的沟道区，以增加第一类杂质的平均掺杂浓度 通道区域中的原子来调节晶体管的阈值电压。

公开(公告)号：US11067620B2

公开(公告)日：2021-07-20

申请号：US16400336

申请日：2019-05-01

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: G01R31/26 ,  G01R27/26

Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.