公开(公告)号：US11557510B2

公开(公告)日：2023-01-17

申请号：US17088002

申请日：2020-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/762 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L23/522

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

公开(公告)号：US11532518B2

公开(公告)日：2022-12-20

申请号：US17178762

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Sheng-Tsung Wang ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L21/033 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/768

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

公开(公告)号：US20220376111A1

公开(公告)日：2022-11-24

申请号：US17484039

申请日：2021-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju Lin ,  Chien Chang ,  Chih-Shiun Chou ,  TaiMin Chang ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Lin-Yu Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

公开(公告)号：US20220367669A1

公开(公告)日：2022-11-17

申请号：US17873771

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

公开(公告)号：US20220359265A1

公开(公告)日：2022-11-10

申请号：US17869337

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/528 ,  H01L23/532 ,  H01L21/76 ,  H01L29/423 ,  H01L29/786 ,  H01L29/40

Abstract: A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.

公开(公告)号：US20220359264A1

公开(公告)日：2022-11-10

申请号：US17812902

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US11456246B2

公开(公告)日：2022-09-27

申请号：US16935135

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

公开(公告)号：US20220278213A1

公开(公告)日：2022-09-01

申请号：US17743992

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

公开(公告)号：US11410876B2

公开(公告)日：2022-08-09

申请号：US17090028

申请日：2020-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/528 ,  H01L23/532 ,  H01L21/76 ,  H01L29/423 ,  H01L29/786 ,  H01L29/40 ,  H01L29/06 ,  H01L21/02

Abstract: A method includes providing a structure having a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the one or more semiconductor channel layers; etching the substrate from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature; forming an S/D contact in the first trench; etching at least a portion of the first dielectric layer resulting in a portion of the S/D contact protruding from the first dielectric layer at the backside of the structure; and depositing a seal layer over the S/D contact, wherein the seal layer caps an air gap between the gate structure and the seal layer.

公开(公告)号：US11387140B2

公开(公告)日：2022-07-12

申请号：US16822383

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate and a gate electrode overlying the substrate. Further, the integrated chip includes a contact layer overlies the substrate and is laterally spaced apart from the gate electrode by a spacer structure. The spacer structure may surround outermost sidewalls of the gate electrode. A hard mask structure may be arranged over the gate electrode and between portions of the spacer structure. A contact via extends through the hard mask structure and contacts the gate electrode. The integrated chip may further include a liner layer that is arranged directly between the hard mask structure and the spacer structure, wherein the liner layer is spaced apart from the gate electrode.