公开(公告)号：US20240404876A1

公开(公告)日：2024-12-05

申请号：US18788772

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju Lin ,  Chien Chang ,  Chih-Shiun Chou ,  Tai Min Chang ,  Yi-Ning Tai ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Lin-Yu Huang

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.

公开(公告)号：US20210375630A1

公开(公告)日：2021-12-02

申请号：US17397206

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chien Chang ,  Yi-Hsiang Chao ,  Hung-Yi Huang ,  Chih-Wei Chang

IPC: H01L21/285 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

公开(公告)号：US20230036693A1

公开(公告)日：2023-02-02

申请号：US17675558

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju Lin ,  Chien Chang ,  Chih-Shiun Chou ,  Tai Min Chang ,  Yi-Ning Tai ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Lin-Yu Huang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L21/311 ,  H01L29/66

Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.

公开(公告)号：US12002867B2

公开(公告)日：2024-06-04

申请号：US17459494

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hung Chu ,  Shuen-Shin Liang ,  Hsu-Kai Chang ,  Tzu Pei Chen ,  Kan-Ju Lin ,  Chien Chang ,  Hung-Yi Huang ,  Sung-Li Wang

IPC: H01L29/45 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/31116 ,  H01L21/823475 ,  H01L23/53242 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US20240136191A1

公开(公告)日：2024-04-25

申请号：US18402018

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chien Chang ,  Yi-Hsiang Chao ,  Hung-Yi Huang ,  Chih-Wei Chang

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

公开(公告)号：US20220376111A1

公开(公告)日：2022-11-24

申请号：US17484039

申请日：2021-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kan-Ju Lin ,  Chien Chang ,  Chih-Shiun Chou ,  TaiMin Chang ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Lin-Yu Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

公开(公告)号：US11901183B2

公开(公告)日：2024-02-13

申请号：US17397206

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chien Chang ,  Yi-Hsiang Chao ,  Hung-Yi Huang ,  Chih-Wei Chang

IPC: H01L21/285 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.