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公开(公告)号:US11469137B2
公开(公告)日:2022-10-11
申请号:US17124184
申请日:2020-12-16
发明人: Shay Reboh , Pablo Acosta Alba , Emmanuel Augendre
IPC分类号: H01L21/762 , H01L21/763 , H01L23/66 , H01L27/12
摘要: A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.
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公开(公告)号:US11466298B2
公开(公告)日:2022-10-11
申请号:US16615427
申请日:2018-05-22
申请人: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , UNIVERSITE CLERMONT AUVERGNE , UNIVERSITE D'EVRY VAL D'ESSONNE
摘要: The present invention relates to a method for preparing phosphorylated keto polyols by biocatalysis and uses thereof.
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公开(公告)号:US20220310394A1
公开(公告)日:2022-09-29
申请号:US17656274
申请日:2022-03-24
发明人: Joël KANYANDEKWE , Cyrille LE ROYER
摘要: A method for forming crystalline SiC-based regions on either side of an N-type transistor channel, including: providing a substrate including a silicon-based layer having a thickness e, forming at least one masking pattern on the silicon-based layer, with the at least one masking pattern having openings, with the openings corresponding to implantation regions of the silicon-based layer, amorphising the silicon-based layer through the openings of the at least one masking pattern, in the implantation regions, to a depth d strictly less than the thickness e, so as to form amorphised implantation regions in the silicon-based layer, implanting carbon into amorphous implantation regions, performing thermal recrystallisation annealing to turn the amorphised implantation regions into crystalline SiC-based regions, the method including: after forming the crystalline SiC-based regions, forming a transistor gate on the silicon-based layer, directly at the edge of the crystalline SiC-based regions.
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公开(公告)号:US11448826B2
公开(公告)日:2022-09-20
申请号:US17305347
申请日:2021-07-06
发明人: Cyrielle Monpeurt , Salim Boutami
摘要: A wavelength demultiplexing device configured so as to spatially distributing the spectral contributions of an incident light beam, when in use, and which includes a linear waveguide and a planar waveguide, formed in a coplanar way and adapted to be optically coupled with one another along a coupling line, by evanescent coupling. Such a device may further include diffraction gratings located in the planar waveguide, to extract light out of the latter.
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公开(公告)号:US20220293934A1
公开(公告)日:2022-09-15
申请号:US17654089
申请日:2022-03-09
发明人: Huu-Dat NGUYEN , Lionel PICARD
IPC分类号: H01M4/525 , H01M4/36 , H01M4/505 , H01M4/485 , H01M4/62 , H01M4/1391 , H01M10/0565 , H01M10/052
摘要: A composite electrode with a solid electrolyte based on polycarbonates includes at least one solid electrolyte consisting of one or more (co)polymers obtained by ring-opening (co)polymerization (ROP) of at least one five- to eight-membered cyclic carbonate and, optionally, of at least one five- to eight-membered lactone, catalyzed with methanesulfonic acid or performed under microwave irradiation in the absence of catalyst. The hydroxyl functions at the end of the chain of the (co)polymer(s) may be protected. The electrode also includes at least one alkali metal or alkaline-earth metal salt and at least one electrode active material. The electrode may include one or more electrically conductive additives and/or one or more binders. The electrode may be used in an electrochemical system such as a lithium battery.
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公开(公告)号:US11444041B2
公开(公告)日:2022-09-13
申请号:US17216794
申请日:2021-03-30
发明人: Hubert Teyssedre , Stefan Landis , Michael May
IPC分类号: H01L23/00 , H01L21/768
摘要: A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.
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公开(公告)号:US11426629B2
公开(公告)日:2022-08-30
申请号:US16756534
申请日:2018-10-19
发明人: Olivier Thomas , Sebastien Brulais , Herve Dang , Laurent Freytrich , Jean-Philippe Gros , Jerome Paulet , Prince Arnaud Ramahefa-Andry
摘要: The invention relates to field of connected sport and specifically a method for quantifying sporting activity implemented by a communication system including: a proximity beacon associated with sports equipment, measuring equipment and a communication node, the method including: (a) communicating between the measuring equipment and the beacon in order to recover a first data packet comprising an identifier relating to a sporting activity associated with the sports equipment; (b) transmitting, to the node, a second data packet comprising the identifier; (c) at the node, determining parameterisation data of the measuring equipment according to the identifier; (d) transmitting, to the measuring equipment, a third data packet 230 comprising said parameterisation data; and (e) at the parameterised measuring equipment, quantifying the sporting activity.
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公开(公告)号:US20220270880A1
公开(公告)日:2022-08-25
申请号:US17652324
申请日:2022-02-24
发明人: Valentin BACQUIE , Nicolas POSSEME
IPC分类号: H01L21/28 , H01L21/3115
摘要: A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies Γi (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.
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公开(公告)号:US11424286B2
公开(公告)日:2022-08-23
申请号:US16937752
申请日:2020-07-24
IPC分类号: H01L27/00 , H01L27/146 , H01L27/15 , H01L31/0392 , H01L31/18 , H01L33/00 , H01L33/58 , H01L33/62
摘要: A wafer-level process includes providing a set of electronic chips, including a stack with a set of matrix arrays of pixels, an interconnect layer electrically connected to the set of matrix arrays of pixels, and a first layer, including vias electrically connected to the interconnect layer. The wafer-level process further includes forming metal pillars on the first layer, the pillars being electrically connected to the vias, and forming a material integrally with the first layer, around the metal pillars. The wafer-level process also includes dicing the electronic chips so as to release the thermomechanical stresses to which the stack is subjected. Finally, the wafer-level process includes making the metal pillars coplanar after dicing the electronic chips.
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150.
公开(公告)号:US11423296B2
公开(公告)日:2022-08-23
申请号:US16095923
申请日:2017-04-27
发明人: Olivier Bichler , Antoine Dupret , Vincent Lorrain
摘要: A device for distributing the convolution coefficients of the least one convolutional kernel of a convolutional neural network is provided, the coefficients being carried by an input bus, to a set of processing units in a processor based on a convolutional-neural-network architecture. The device comprises at least one switching network that is controlled by at least one control unit, the switching network comprising a set of switches that are arranged to apply circular shifts to at least one portion of the input bus. For each convolution kernel, each control unit is configured to dynamically control certain at least of the switches of the switching networks in response to an input event applied to the convolution kernel and at least one parameter representing the maximum size of the convolution kernels.
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