METHOD FOR PRODUCING A MICROELECTRONIC DEVICE

    公开(公告)号:US20220310394A1

    公开(公告)日:2022-09-29

    申请号:US17656274

    申请日:2022-03-24

    IPC分类号: H01L21/04 H01L29/66 H01L29/08

    摘要: A method for forming crystalline SiC-based regions on either side of an N-type transistor channel, including: providing a substrate including a silicon-based layer having a thickness e, forming at least one masking pattern on the silicon-based layer, with the at least one masking pattern having openings, with the openings corresponding to implantation regions of the silicon-based layer, amorphising the silicon-based layer through the openings of the at least one masking pattern, in the implantation regions, to a depth d strictly less than the thickness e, so as to form amorphised implantation regions in the silicon-based layer, implanting carbon into amorphous implantation regions, performing thermal recrystallisation annealing to turn the amorphised implantation regions into crystalline SiC-based regions, the method including: after forming the crystalline SiC-based regions, forming a transistor gate on the silicon-based layer, directly at the edge of the crystalline SiC-based regions.

    Process of realization of an area of individualization of an integrated circuit

    公开(公告)号:US11444041B2

    公开(公告)日:2022-09-13

    申请号:US17216794

    申请日:2021-03-30

    IPC分类号: H01L23/00 H01L21/768

    摘要: A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.

    METHOD OF FORMING THE SPACERS OF A TRANSISTOR GATE

    公开(公告)号:US20220270880A1

    公开(公告)日:2022-08-25

    申请号:US17652324

    申请日:2022-02-24

    IPC分类号: H01L21/28 H01L21/3115

    摘要: A method is provided for forming spacers of a gate of a transistor, including: providing an active layer surmounted by a gate; forming a dielectric layer covering the gate and the active layer, the dielectric layer having lateral portions and basal portions; anisotropically modifying the basal portions by implantation of light ions, forming modified basal portions; and removing the modified basal portions by selective etching, so as to form the spacers on the lateral flanks of the gate from the unmodified lateral portions, in which, before the removing step, the anisotropic modification of the basal portions includes n successive implantation phases having implantation energies Γi (i=1 . . . n) which are distinct from each other, the n phases being configured to implant the light ions at different nominal implantation depths.

    Device and method for distributing convolutional data of a convolutional neural network

    公开(公告)号:US11423296B2

    公开(公告)日:2022-08-23

    申请号:US16095923

    申请日:2017-04-27

    IPC分类号: G06N3/08 G06N3/04 G06N3/063

    摘要: A device for distributing the convolution coefficients of the least one convolutional kernel of a convolutional neural network is provided, the coefficients being carried by an input bus, to a set of processing units in a processor based on a convolutional-neural-network architecture. The device comprises at least one switching network that is controlled by at least one control unit, the switching network comprising a set of switches that are arranged to apply circular shifts to at least one portion of the input bus. For each convolution kernel, each control unit is configured to dynamically control certain at least of the switches of the switching networks in response to an input event applied to the convolution kernel and at least one parameter representing the maximum size of the convolution kernels.