公开(公告)号：US11862271B2

公开(公告)日：2024-01-02

申请号：US16418833

申请日：2019-05-21

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yannis Jallamion-Grive ,  Cyrille Nicolas Dray

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/27 ,  G06F11/10 ,  G11C29/34 ,  G11C29/02 ,  G11C29/18

CPC classification number: G11C29/42 ,  G06F11/102 ,  G06F11/106 ,  G06F11/27 ,  G11C29/025 ,  G11C29/34 ,  G11C29/781 ,  G11C29/802 ,  G11C2029/1802

Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

公开(公告)号：US11861368B2

公开(公告)日：2024-01-02

申请号：US17752060

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Michael Brian Schinzler ,  Yasuo Ishii ,  Jatin Bhartia ,  Sumanth Chengad Raghu

IPC: G06F9/38 ,  G06F21/50 ,  G06F9/48

CPC classification number: G06F9/3848 ,  G06F9/3844 ,  G06F9/3806 ,  G06F9/48 ,  G06F21/50

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

公开(公告)号：US20230418609A1

公开(公告)日：2023-12-28

申请号：US17851266

申请日：2022-06-28

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Alexander Cole SHULYAK ,  Yasuo ISHII ,  Houdhaifa BOUZGUARROU

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3861

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.

公开(公告)号：US11853755B2

公开(公告)日：2023-12-26

申请号：US17754189

申请日：2020-07-30

Applicant: ARM LIMITED

Inventor： Eric Ola Harald Liljedahl

IPC: G06F9/30 ,  G06F9/52

CPC classification number: G06F9/30021 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/526

Abstract: Apparatuses, methods of data processing, complementary instructions and programs related to atomic range-compare-and-modify operations are disclosed. Data processing operations are performed in response to received instructions, wherein the data processing operations comprise an atomic range-compare-and-modify operation, which receives indications of a data value storage location, a range start, and a range size and, as an atomic set of steps, reads a base value stored at the data value storage location, determines an in-range condition to be true when the base value is within a request range having a lower bound being the range start and an upper bound being the range start plus the range size, and when the in-range condition is true, modify the base value to an updated base value. Reduced contention between processes accessing the same data value storage location and range of locations is thus supported.

公开(公告)号：US11853226B2

公开(公告)日：2023-12-26

申请号：US16624430

申请日：2018-05-15

Applicant: ARM LIMITED

Inventor： Andrew Brookfield Swaine

IPC: G06F12/00 ,  G06F12/1036 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/0864 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/657

Abstract: An apparatus has an address translation cache (12, 16) having a number of cache entries (40) for storing address translation data which depends on one or more page table entries of page tables. Control circuitry (50) is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry (50) selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.

公开(公告)号：US11853220B2

公开(公告)日：2023-12-26

申请号：US17501272

申请日：2021-10-14

Applicant: Arm Limited

Inventor： Natalya Bondarenko ,  Stefano Ghiggini ,  Damien Matthieu Valentin Cathrine ,  Ugo Castorina

IPC: G06F12/0862 ,  G06F12/0891 ,  G06F13/16 ,  G06F12/02 ,  G06F18/214

CPC classification number: G06F12/0862 ,  G06F12/0238 ,  G06F12/0891 ,  G06F13/1621 ,  G06F13/1668 ,  G06F18/214

Abstract: An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.

公开(公告)号：US20230410896A1

公开(公告)日：2023-12-21

申请号：US17844551

申请日：2022-06-20

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Arjun Singh ,  Ayush Kulshrestha

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

公开(公告)号：US20230401667A1

公开(公告)日：2023-12-14

申请号：US18249342

申请日：2021-10-19

Applicant: Arm Limited

Inventor： Sandeep KAKARLAPUDI ,  Andreas ENGH-HALSTVEDT ,  Frank Klaeboe LANGTIND

IPC: G06T1/20 ,  G06T15/40 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T15/40 ,  G06T11/40 ,  G06T2210/12

Abstract: A method of operating a graphics processor to process sets of geometry to generate an output. Each set of geometry is associated with lower level geometry including vertex data to be used when rendering the geometry as well a separate higher level representation of the geometry. The higher level representations of the geometry can be obtained by the graphics processor independently of the other, lower level geometry and used to determine which sets of geometry should be processed for which regions of the output. Once this determination is made, the regions can be rendered by obtaining and processing the lower level geometry accordingly.

公开(公告)号：US20230396059A1

公开(公告)日：2023-12-07

申请号：US17833249

申请日：2022-06-06

Applicant: Arm Limited

Inventor： Ranabir Dey ,  Gayathri Gandhi ,  Akshaykumar V Jabi ,  Vipul Patel Pursottam

IPC: H02H9/00 ,  H02H1/00

CPC classification number: H02H9/00 ,  H02H1/0007

Abstract: Various implementations described herein are related to a device with a bias generator that receives a pad control signal, receives an output pad voltage as a pad feedback signal from an output pad, and provides bias voltage signals based on the pad control signal and the pad feedback signal. The device may have a bias driver that receives the bias signals from the bias generator and provides the output pad voltage to the output pad based on the bias signals. The device may have a pad voltage detector that receives the output pad voltage as the pad feedback signal from the output pad and provides the pad control signal to the bias generator based on the pad feedback signal.

公开(公告)号：US11837543B2

公开(公告)日：2023-12-05

申请号：US17006695

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L27/0688

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.