公开(公告)号：US11233045B2

公开(公告)日：2022-01-25

申请号：US17265541

申请日：2019-09-04

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/866

Abstract: A transient voltage suppression device includes a substrate; a first conductivity type well region disposed in the substrate and comprising a first well and a second well; a third well disposed on the substrate, a bottom part of the third well extending to the substrate; a fourth well disposed in the first well; a first doped region disposed in the second well; a second doped region disposed in the third well; a third doped region disposed in the fourth well; a fourth doped region disposed in the fourth well; a fifth doped region extending from inside of the fourth well to the outside of the fourth well, a portion located outside the fourth well being located in the first well; a sixth doped region disposed in the first well; a seventh doped region disposed below the fifth doped region and in the first well.

公开(公告)号：US20210242305A1

公开(公告)日：2021-08-05

申请号：US17265565

申请日：2019-08-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Guipeng Sun

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

公开(公告)号：US20210234041A1

公开(公告)日：2021-07-29

申请号：US17262882

申请日：2019-07-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device and method for manufacturing same. The semiconductor device comprises: a drift region (120); an isolation structure (130) contacting the drift region (120), the isolation structure (130) comprising a first isolation layer (132), a hole etch stop layer (134) on the first isolation layer (132), and a second isolation layer (136) on the hole etch stop layer (134); and a hole field plate (180) provided above the hole etch stop layer (134) and contacting the hole etch stop layer (134).

公开(公告)号：US11075292B2

公开(公告)日：2021-07-27

申请号：US16864263

申请日：2020-05-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tse-Huang Lo

IPC: H01L29/739 ,  H01L21/265 ,  H01L21/027 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: An insulated gate bipolar transistor includes a substrate; a first conductivity type base disposed on the substrate and having a first trench; a first conductivity type buffer region disposed in the first conductivity type base; a collector doped region having a second conductivity type and disposed in the first conductivity type base; a second conductivity type base to which the first trench extends downwardly; a gate oxide layer disposed on an inner surface of the first trench; a polysilicon gate disposed inside the gate oxide layer; an emitter doped region having a first conductivity type and disposed in the second conductivity type base and under the first trench; a conductive plug extending downwardly from above the first trench and contacting the second conductivity type base; and an insulating oxide layer filled in the first trench, the insulating oxide layer insulating and isolating the polysilicon gate from the emitter doped region.

公开(公告)号：US20210143274A1

公开(公告)日：2021-05-13

申请号：US17263207

申请日：2019-07-25

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Tse-huang LO

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

Abstract: An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.

公开(公告)号：US20200350420A1

公开(公告)日：2020-11-05

申请号：US16957600

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

公开(公告)号：US20200343810A1

公开(公告)日：2020-10-29

申请号：US16959015

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Shen XU ,  Minggang CHEN ,  Hao WANG ,  Jinyu XIAO ,  Wei SU ,  Weifeng SUN ,  Longxing SHI

IPC: H02M1/38 ,  H02M3/335 ,  H02M1/08

Abstract: An automatic dead zone time optimization system in a primary-side regulation flyback power supply CCM mode, comprising a closed loop formed by a control system, consisting of a single output DAC midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a PWM driving module, and a controlled synchronous rectification primary-side regulation flyback converter. By means of a DAC Sampling mechanism, a primary-side current is sampled to calculate a secondary-side average current, so as to obtain a primary-side average current Imid_p and a secondary-side average current Is(tmid) in the case of CCM; a secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time td; and finally, the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time td.

公开(公告)号：US20200336070A1

公开(公告)日：2020-10-22

申请号：US16959001

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Rongrong TAO ,  Hao WANG ,  Jinyu XIAO ,  Wei SU ,  Shen XU ,  Longxing SHI

IPC: H02M3/335 ,  H03K5/24

Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a threshold value Tset, calculating a time interval Ttap between adjacent zero points during a present conducting time, outputting a switch-off signal at zero points, and comparing the time interval Ttap with the preset threshold value Tset; when Ttap>Tset, he present switch-off time to be less than a switch-off time of a previous cycle, outputting a switch-on signal; when Ttap=0, controlling the present switch-off time to be greater than a switch-off time of the previous cycle, outputting a switch-on signal; and when 0

公开(公告)号：US20200335498A1

公开(公告)日：2020-10-22

申请号：US16755817

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L27/088 ,  H01L29/78

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

公开(公告)号：US20200328689A1

公开(公告)日：2020-10-15

申请号：US16915524

申请日：2020-06-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Shen XU ,  Wei WANG ,  Feng LIN ,  Boyong HE ,  Wei SU ,  Weifeng SUN ,  Longxing SHI

IPC: H02M3/335 ,  G01R19/165 ,  H03K5/24

Abstract: Provided is a dynamic control method that turns off a primary-side switching transistor when an output voltage exceeds an upper limit, and control the switching of a secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly.