公开(公告)号：US20090027967A1

公开(公告)日：2009-01-29

申请号：US12175609

申请日：2008-07-18

Applicant: Chang-hyun LEE

Inventor： Chang-hyun LEE

IPC: G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3454

Abstract: A memory system includes a flash memory device and a memory controller for controlling the flash memory device. The flash memory device includes a cell string and a selection transistor connected in series to the cell string. The cell string includes multiple series-connected memory cells. The selection transistor has the same structure as a memory cell of the series-connected memory cells, and is programmed through channel hot electron injection.

Abstract translation: 存储器系统包括闪存器件和用于控制闪存器件的存储器控​​制器。 闪存器件包括与单元串串联连接的单元串和选择晶体管。 单元串包括多个串联存储单元。 选择晶体管具有与串联存储单元的存储单元相同的结构，并且通过通道热电子注入来编程。

公开(公告)号：US20090016112A1

公开(公告)日：2009-01-15

申请号：US12236916

申请日：2008-09-24

Applicant: Chang Hyun Lee

Inventor： Chang Hyun Lee

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp

Abstract translation: 非易失性存储器件包括其中的闪存单元阵列和电压发生器。 电压发生器被配置为在闪速存储器编程操作期间产生编程电压（Vpgm），通过电压（Vpass），阻断电压（Vblock）和去耦电压（Vdcp）。 阻塞电压产生在抑制非选择存储单元的无意编程的水平。 该阻塞电压的电压电平被设定为使得Vdcp

公开(公告)号：US20080240043A1

公开(公告)日：2008-10-02

申请号：US12050341

申请日：2008-03-18

Applicant: Chang-Hyun LEE ,  Sung-Jea Ko ,  Yun-Je Oh ,  Tae-Sung Park ,  Jeong-Rok Park ,  Jeong-Seok Choi ,  Young-Hun Joo ,  Hye-Soo Kim ,  Kyung-Ho Chae

Inventor： Chang-Hyun LEE ,  Sung-Jea Ko ,  Yun-Je Oh ,  Tae-Sung Park ,  Jeong-Rok Park ,  Jeong-Seok Choi ,  Young-Hun Joo ,  Hye-Soo Kim ,  Kyung-Ho Chae

IPC: H04Q7/00

CPC classification number: H04W36/30 ,  H04W36/26

Abstract: A system and method for performing a handover of a mobile station (MS) by considering Quality of Service (QoS) in a broadband mobile communication system. The method can include the steps of: receiving information about one or more neighbor base stations and reception strengths for the neighbor base stations from a Serving Radio Access System (RAS) currently communicating with the MS; extracting a value of a specific field from the received information about the neighbor base stations; combining the extracted value of the specific field with the reception strengths to thereby obtain combined values, and selecting a maximum value among the combined values; and transmitting a handover (handoff) request message to a base station corresponding to the selected maximum value. The system includes an MS that analyzes information about neighbor stations received in a Mobile Neighbor Base-station Advertisement (MOB_NBR_ADV) message to select a target RAS.

Abstract translation: 一种通过考虑宽带移动通信系统中的服务质量（QoS）来执行移动台（MS）的切换的系统和方法。 该方法可以包括以下步骤：从当前与MS通信的服务无线电接入系统（RAS）接收关于一个或多个相邻基站的信息和相邻基​​站的接收强度; 从接收到的关于邻近基站的信息中提取特定字段的值; 将所提取的特定字段的值与接收强度组合，从而获得组合值，并且选择组合值中的最大值; 以及向对应于所选择的最大值的基站发送切换（切换）请求消息。 该系统包括分析在移动邻居基站广播（MOB_NBR_ADV）消息中接收的关于相邻站的信息以选择目标RAS的MS。

公开(公告)号：US07412164B2

公开(公告)日：2008-08-12

申请号：US10425699

申请日：2003-04-29

Applicant: Jeong-Seok Choi ,  Yun-Je Oh ,  Jun-Ho Koh ,  Chang-Hyun Lee ,  Byung-Jik Kim ,  Jeong-Rok Park

Inventor： Jeong-Seok Choi ,  Yun-Je Oh ,  Jun-Ho Koh ,  Chang-Hyun Lee ,  Byung-Jik Kim ,  Jeong-Rok Park

IPC: H04B10/00

CPC classification number: H04L1/22

Abstract: A photoelectric cross-connect system for an optical-communication system minimizes service recovery time when an error is generated. A plurality of nodes are connected by an optical-transmission line wherein each nodes automatically recognizes a data rate of an input signal and communicates over a redundant channel with an adjacent node when there is a certain type of error. An optical-receiving unit receives an optical signal performs O/E conversion. A main optical-transmitting unit recovers clock and data signals according to the converted signal and sets a data rate according to the converted signal for subsequent transmission; a redundant optical-transmitting unit recovers a clock and data according to the converted signal and sets a data rate according to the converted signal for subsequent transmission A switch provides selectively connection state between the optical-receiving unit and the main optical-transmitting unit and between the optical-receiving unit and the redundant optical-transmitting unit.

Abstract translation: 用于光通信系统的光电交叉连接系统在产生错误时将服务恢复时间最小化。 多个节点通过光传输线连接，其中每个节点自动识别输入信号的数据速率，并且当存在某种类型的错误时，通过冗余信道与相邻节点进行通信。 光接收单元接收执行O / E转换的光信号。 主光传输单元根据转换的信号恢复时钟和数据信号，并根据转换的信号设置数据速率用于随后的传输; 冗余光传输单元根据转换的信号恢复时钟和数据，并根据转换的信号设置数据速率用于后续发送。A交换机选择性地提供光接收单元和主光传输单元之间的连接状态，以及 光接收单元和冗余光发射单元。

公开(公告)号：US20080135912A1

公开(公告)日：2008-06-12

申请号：US11976389

申请日：2007-10-24

Applicant: Chang-Hyun Lee ,  Jung-dal Choi

Inventor： Chang-Hyun Lee ,  Jung-dal Choi

IPC: H01L29/788 ,  H01L21/8247

CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

Abstract translation: 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

公开(公告)号：US20080116668A1

公开(公告)日：2008-05-22

申请号：US11642449

申请日：2006-12-20

Applicant: Chang Hyun Lee

Inventor： Chang Hyun Lee

IPC: B60R21/20

CPC classification number: B60R21/20 ,  B60R21/201 ,  B60R21/2037

Abstract: An air bag apparatus includes: a supporting plate; an air bag case mounted on the supporting plate such that a space is formed therein; an air bag cushion installed in the space and attached to the supporting plate; an inflator for supplying a gas to the air bag cushion, the inflator being mounted at the supporting plate; and a clamping device for clamping a middle portion of the air bag cushion, the clamping device being coupled with the supporting plate. The inflator may supply the gas to side portions of the air bag, such that the side portions expand for a predetermined time while the middle portion is clamped by the clamping device, and when the inflating force of the air bag overcomes the clamping force, the middle portion expands.

Abstract translation: 气囊装置包括：支撑板; 安装在所述支撑板上的气囊壳体，以便在其中形成空间; 安装在该空间中并安装在支撑板上的气囊垫; 用于向气囊垫提供气体的充气机，所述充气机安装在所述支撑板上; 以及用于夹持气囊衬垫的中间部分的夹紧装置，夹紧装置与支撑板联接。 充气机可以将气体供应到气囊的侧部，使得侧部膨胀预定时间，同时中间部分被夹紧装置夹紧，并且当气囊的膨胀力克服夹紧力时， 中间部分展开。

公开(公告)号：US20080089131A1

公开(公告)日：2008-04-17

申请号：US11953263

申请日：2007-12-10

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp

Abstract translation: 非易失性存储器件包括其中的闪存单元阵列和电压发生器。 电压发生器被配置为在闪速存储器编程操作期间产生编程电压（Vpgm），通过电压（Vpass），阻断电压（Vblock）和去耦电压（Vdcp）。 阻塞电压产生在抑制非选择存储单元的无意编程的水平。 该阻塞电压的电压电平被设定为使得Vdcp

公开(公告)号：US07230294B2

公开(公告)日：2007-06-12

申请号：US10975933

申请日：2004-10-28

Applicant: Chang-Hyun Lee ,  Kyu-Charn Park

Inventor： Chang-Hyun Lee ,  Kyu-Charn Park

IPC: G11C7/00 ,  H01L29/76

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

公开(公告)号：US20070104011A1

公开(公告)日：2007-05-10

申请号：US11507511

申请日：2006-08-22

Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Chang-Hyun Lee ,  Jang-Sik Lee ,  Vie-Na Kim

Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Chang-Hyun Lee ,  Jang-Sik Lee ,  Vie-Na Kim

IPC: G11C8/00

CPC classification number: G11C8/14 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.

Abstract translation: 电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于 与第一区域的顶表面不同的水平。 单元阵列还包括跨越第一区域的多个字线。 单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

公开(公告)号：US20070103990A1

公开(公告)日：2007-05-10

申请号：US11611972

申请日：2006-12-18

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

Abstract: An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

Abstract translation: 电可擦除电荷陷阱非易失性存储单元具有初始阈值电压，高于初始阈值电压的编程电压和低于编程阈值电压但高于初始阈值电压的擦除阈值电压。 可以通过施加足以将晶体管的阈值电压从编程阈值电压降低到低于编程阈值电压的擦除阈值电压的时间间隔施加擦除电压来擦除编程的电可擦除电荷陷阱非易失性存储器单元， 但高于初始阈值电压。 可以通过使用从初始时间间隔增加或减少的时间间隔重复执行耐久性测试来获得时间间隔，以获得满足耐久性规范的时间间隔，或允许成功执行读取。