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    Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same
    1.
    发明授权
    Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same 有权
    在衬底上具有半导体图案的存储器件及其制造方法

    公开(公告)号：US09324727B2

    公开(公告)日：2016-04-26

    申请号：US14176332

    申请日：2014-02-10

    Applicant: Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

    Inventor： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

    IPC: H01L27/115 ,  H01L21/762 ,  H01L23/48 ,  H01L29/788

    CPC classification number: H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

    Abstract: A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

    Abstract translation: 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

    Nonvolatile memory devices
    2.
    发明授权
    Nonvolatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US08629489B2

    公开(公告)日：2014-01-14

    申请号：US13357350

    申请日：2012-01-24

    Applicant: Chang-Hyun Lee ,  Jung-Dal Choi

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi

    IPC: H01L29/76

    CPC classification number: H01L27/1052 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers.

    Abstract translation: 非易失性存储器件包括串选择晶体管，多个存储单元晶体管和与串选择晶体管和多个存储单元晶体管串联电连接的接地选择晶体管。 在存储单元晶体管的沟道和源极/漏极区的边界处形成第一杂质层。 相对于存储单元晶体管的源/漏区，第一杂质层掺杂有相反导电类型的杂质。 第二杂质层形成在串选择晶体管的沟道和漏极区之间的边界处，并且在地选择晶体管的沟道和源极区之间形成。 第二杂质层掺杂有与第一杂质层相同的导电类型杂质，并且具有比第一杂质层更高的杂质浓度。

    Methods of fabricating non-volatile memory devices including double diffused junction regions
    3.
    发明授权
    Methods of fabricating non-volatile memory devices including double diffused junction regions 有权
    制造包括双扩散连接区域的非易失性存储器件的方法

    公开(公告)号：US08324052B2

    公开(公告)日：2012-12-04

    申请号：US13010583

    申请日：2011-01-20

    Applicant: Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    Inventor： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    IPC: H01L21/331

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

    Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

    Abstract translation: 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。

    METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS
    4.
    发明申请
    METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS 有权
    制造非易失性记忆装置的方法，包括双重扩散结区

    公开(公告)号：US20110111570A1

    公开(公告)日：2011-05-12

    申请号：US13010583

    申请日：2011-01-20

    Applicant: Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    Inventor： Dong-Yean Oh ,  Jai-Hyuk Song ,  Chang-Sub Lee ,  Chang-Hyun Lee ,  Hyun-Jae Kim

    IPC: H01L21/8234

    CPC classification number: H01L27/11521 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11524

    Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

    Abstract translation: 非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。 第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。 第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度 与其紧邻的多个存储单元门。 还讨论了相关的制造方法。

    NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件

    公开(公告)号：US20110079838A1

    公开(公告)日：2011-04-07

    申请号：US12961678

    申请日：2010-12-07

    Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Chang-Seok Kang ,  Jin-Taek Park ,  Byeong-In Choe

    IPC: H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42352 ,  H01L29/7851 ,  H01L29/792

    Abstract: A method of fabricating a semiconductor device includes forming a fin-shaped active region including opposing sidewalls and a surface therebetween protruding from a substrate, forming a gate structure on the surface of the active region, and performing an ion implantation process to form source/drain regions in the active region at opposite sides of the gate structure. The source/drain regions respectively include a first impurity region in the surface of the active region and second impurity regions in the opposing sidewalls of the active region. The first impurity region has a doping concentration that is greater than that of the second impurity regions. Related devices are also discussed.

    Abstract translation: 一种制造半导体器件的方法包括：形成鳍状有源区，包括相对的侧壁和从衬底突出的表面，在有源区的表面上形成栅极结构，并执行离子注入工艺以形成源极/漏极 在栅极结构的相对侧的有源区中的区域。 源极/漏极区域分别包括有源区的表面中的第一杂质区域和有源区的相对侧壁中的第二杂质区。 第一杂质区域的掺杂浓度大于第二杂质区域的掺杂浓度。 还讨论了相关设备。

    Method of programming a flash memory device
    7.
    发明授权
    Method of programming a flash memory device 有权
    Flash存储设备编程方法

    公开(公告)号：US07894266B2

    公开(公告)日：2011-02-22

    申请号：US12236916

    申请日：2008-09-24

    Applicant: Chang-Hyun Lee

    Inventor： Chang-Hyun Lee

    IPC: G11C16/04

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp

    Abstract translation: 非易失性存储器件包括其中的闪存单元阵列和电压发生器。 电压发生器被配置为在闪速存储器编程操作期间产生编程电压（Vpgm），通过电压（Vpass），阻断电压（Vblock）和去耦电压（Vdcp）。 阻塞电压产生在抑制非选择存储单元的无意编程的水平。 该阻塞电压的电压电平被设定为使得Vdcp

    Nonvolatile memory devices and methods of operating same to inhibit parasitic charge accumulation therein
    8.
    发明授权
    Nonvolatile memory devices and methods of operating same to inhibit parasitic charge accumulation therein 有权
    非易失性存储器件及其操作方法，以抑制其中的寄生电荷积聚

    公开(公告)号：US07864582B2

    公开(公告)日：2011-01-04

    申请号：US12191434

    申请日：2008-08-14

    Applicant: Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

    Inventor： Chang-Hyun Lee ,  Jung-Dal Choi ,  Young-Ho Lim ,  Kang-Deog Suh

    IPC: G11C16/06

    CPC classification number: G11C16/0483 ,  G11C16/16

    Abstract: Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells.

    Abstract translation: 操作电荷阱非易失性存储装置的方法包括通过选择性地擦除第一串中的第一多个非易失性存储单元，然后选择性地擦除第一串中的第二多个非易失性存储单元来擦除第一串非易失性存储单元的操作， 其可以与第一多个非易失性存储器单元交错。 选择性地擦除第一多个非易失性存储单元的操作可以包括擦除第一多个非易失性存储单元，同时在禁止擦除第二多个非易失性存储单元的阻塞条件下同时偏置第二多个非易失性存储单元。 选择性地擦除第二多个非易失性存储单元的操作可以包括擦除第二多个非易失性存储单元，同时在禁止擦除第一多个非易失性存储单元的阻塞条件下同时偏置第一多个非易失性存储单元。

    Memory device and method of fabricating the same
    9.
    发明申请
    Memory device and method of fabricating the same 有权
    存储器件及其制造方法

    公开(公告)号：US20100327371A1

    公开(公告)日：2010-12-30

    申请号：US12805962

    申请日：2010-08-26

    Applicant: Chang-Hyun Lee ,  Jung-dal Choi

    Inventor： Chang-Hyun Lee ,  Jung-dal Choi

    IPC: H01L27/088 ,  H01L21/8239

    CPC classification number: H01L27/115 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    Abstract: A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

    Abstract translation: 一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域 晶体管是第一类型。 第一种类型可以是n型或p型。 非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管 串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

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