公开(公告)号：US10725960B2

公开(公告)日：2020-07-28

申请号：US16371664

申请日：2019-04-01

Applicant: Microchip Technology Incorporated

Inventor： Morten Werner Lund ,  Lloyd Clark ,  Odd Magne Reitan

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  G06F9/54 ,  G06F13/362 ,  G06F3/041 ,  G09G5/00

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

公开(公告)号：US10725939B2

公开(公告)日：2020-07-28

申请号：US15894007

申请日：2018-02-12

Applicant: Microchip Technology Incorporated

Inventor： Atish Ghosh ,  Mark Gordon ,  Ken Nagai ,  Larisa Troyegubova

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38

Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element.

公开(公告)号：US20200211936A1

公开(公告)日：2020-07-02

申请号：US16720269

申请日：2019-12-19

Applicant: Microchip Technology Incorporated

Inventor： Rangsun Kitnarong ,  Vichanart Nimibutr ,  Pattarapon Poolsup ,  Chanyuth Junjuewong

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H05K1/18 ,  H01L23/31

Abstract: Methods are disclosed for forming flat leads packages (e.g., QFP or SOT packages) having leads coated with a solder-enhancing material for improved solder mounting to a PCB or other structure. The method may include forming a flat leads package structure including an array of encapsulated IC structures formed on a common leadframe. An isolation cutting process may be performed to electrically isolate the IC structures from each other and define a plurality of leadframe leads extending from each IC structure. After the isolation cutting process, an immersion coating process is performed to coat exposed surfaces of the leadframe leads, including the full surface area of a distal end of each leadframe lead. The coating (e.g., tin coating) covering the distal ends of the leadframe leads may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.

公开(公告)号：US10664435B2

公开(公告)日：2020-05-26

申请号：US15970726

申请日：2018-05-03

Applicant: Microchip Technology Incorporated

Inventor： Morten Werner Lund ,  Lloyd Clark ,  Odd Magne Reitan

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  G06F9/54 ,  G06F13/362 ,  G06F3/041 ,  G09G5/00

Abstract: The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

公开(公告)号：US10658453B2

公开(公告)日：2020-05-19

申请号：US16037889

申请日：2018-07-17

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Yaojian Leng ,  Greg Stom

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/02

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure may include forming a trench in a dielectric region; forming a TFR element in the trench, the TFR element including a laterally-extending TFR region and a TFR ridge extending upwardly from a laterally-extending TFR region; depositing at least one metal layer over the TFR element; and patterning the at least one metal layer and etching the at least one metal layer using a metal etch to define a pair of metal TFR heads over the TFR element, wherein the metal etch also removes at least a portion of the upwardly-extending TFR ridge. The method may also include forming at least one conductive TFR contact extending through the TFR element and in contact with a respective TFR head to thereby increase a conductive path between the respective TFR head and the TFR element.

公开(公告)号：US20200151336A1

公开(公告)日：2020-05-14

申请号：US16364391

申请日：2019-03-26

Applicant: Microchip Technology Incorporated

Inventor： Kerry Maletsky ,  David Paul Arnold ,  Nicolas Auguste Constant Schieli ,  Bryan Hunt

IPC: G06F21/57 ,  G06F21/34

Abstract: Systems, methods, and devices of the disclosure relate, generally, to secure boot assist for devices. In one or more embodiments, a first device includes firmware that needs to be verified as secure as part of a secure boot process, and a second device assists the first device to secure the secure boot process. In some embodiments the second device verifies security of the firmware responsive to security data provided by the first device, or verifies security of a program provided by the first device, the program for verifying security of the firmware. In some embodiments the second device provides a program for verifying security of the firmware to the first device.

公开(公告)号：US20200083794A1

公开(公告)日：2020-03-12

申请号：US16428094

申请日：2019-05-31

Applicant: Microchip Technology Incorporated

Inventor： Santosh Manjunath Bhandarkar ,  Alex Dumais

IPC: H02M1/08 ,  H02M3/157 ,  H03K5/24

Abstract: Adaptive slope compensation for current mode control in a switch mode power supply converter is computed for every switching cycle based upon the input voltage and duty-cycle whereby the quality factor is maintained at a constant value. A digital signal processing (DSP) capable microcontroller comprises a voltage loop compensator and generates a desired current reference for every switching cycle. Slope calculations are adapted for switching frequency, inductance value, current circuit gain, etc. The slope calculation result is applied to a pulse-digital-modulation (PDM) digital-to-analog converter (DAC) capable of changing its output levels at a very fast rate compared to the power supply switching frequency whereby the required current slope is provided within the switching period. Actual inductor current may be used to compare against the slope reference, thereby taking care of changes in the inductance values under load. The slope levels are automatically changed when the switching frequency is changed.

公开(公告)号：US10581436B1

公开(公告)日：2020-03-03

申请号：US16270208

申请日：2019-02-07

Applicant: Microchip Technology Incorporated

Inventor： Pancham R. Patel ,  Esmael Heidari

IPC: H03K21/02 ,  H03K21/10 ,  H03K21/08 ,  H03L7/099 ,  H03K19/20

Abstract: Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wherein the MMD is configured to enter the common state regardless of a divisor value applied to the MMD. The method may further include receiving an integer value at the MMD. Further, the method may include setting the divisor value equal to the integer value. The method may also include receiving an input signal at a first frequency and generating an output signal at a second, lower frequency based on the divisor value. The method may also include receiving a second integer value at the MMD. The method may further include setting the divisor value equal to the second integer value in response to a detected current state of the MMD matching the common state for the MMD.

公开(公告)号：US20200012313A1

公开(公告)日：2020-01-09

申请号：US16143841

申请日：2018-09-27

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Aditya Nukala

IPC: G06F1/14 ,  G06F1/08 ,  G06F11/16 ,  G06F1/10

Abstract: A system for testing a clock monitor includes a fault injection circuit, a control circuit, and a clock monitor circuit to evaluate a clock source signal from a clock source. The fault injection circuit is to modify or replace the clock source signal from the clock source to yield a modified clock signal, and send the modified clock signal to the clock monitor circuit. The clock monitor circuit is to receive an input clock signal, determine whether the input clock signal indicates a faulty clock source, and issue a clock corrective action if the input clock signal indicates a faulty clock source. The control circuit is to monitor for the clock corrective action, and determine, based on whether the clock corrective action is issued, whether the clock monitor circuit is operating correctly.

公开(公告)号：US20190392899A1

公开(公告)日：2019-12-26

申请号：US16013631

申请日：2018-06-20

Applicant: Microchip Technology Incorporated

Inventor： Sonu Daryanani ,  Matthew G. Martin ,  Gilles Festes

IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/56 ,  H01L27/11521 ,  H01L29/66

Abstract: Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage VCGR to the control gate.