公开(公告)号：US11533077B2

公开(公告)日：2022-12-20

申请号：US17023169

申请日：2020-09-16

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Carl Werner

IPC: H04B3/32

Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

公开(公告)号：US11526632B2

公开(公告)日：2022-12-13

申请号：US16997661

申请日：2020-08-19

Applicant: Rambus Inc.

Inventor： Craig E. Hampel ,  Liji Gopalakrishnan ,  John Eric Linstadt ,  Steven C. Woo

IPC: G06F21/75 ,  H04L9/00 ,  G06F12/14 ,  G06F21/60 ,  G06F3/06

Abstract: Methods and systems for enabling secure memory transactions in a memory controller are disclosed. Responsive to determining that an incoming request is for a secure memory transaction, the incoming request is placed in a secure request container. The memory container then enters a state where re-ordering between requests for secure memory transactions placed in the secure request container and requests for non-secure memory transactions from other containers is prevented in a scheduling queue.

公开(公告)号：US11520633B2

公开(公告)日：2022-12-06

申请号：US16947191

申请日：2020-07-22

Applicant: Rambus Inc.

Inventor： Keith Lowery

IPC: G06F9/50 ,  G06F8/41 ,  G06F9/30 ,  G06F9/38 ,  G06F12/02

Abstract: A method and system for thread aware, class aware, and topology aware memory allocations. Embodiments include a compiler configured to generate compiled code (e.g., for a runtime) that when executed allocates memory on a per class per thread basis that is system topology (e.g., for non-uniform memory architecture (NUMA)) aware. Embodiments can further include an executable configured to allocate a respective memory pool during runtime for each instance of a class for each thread. The memory pools are local to a respective processor, core, etc., where each thread executes.

公开(公告)号：US20220366960A1

公开(公告)日：2022-11-17

申请号：US17852286

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G11C29/02 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US20220350763A1

公开(公告)日：2022-11-03

申请号：US17748762

申请日：2022-05-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G11C5/04 ,  G11C7/10 ,  G06F13/16

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US11489703B2

公开(公告)日：2022-11-01

申请号：US16953225

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H04L25/03 ,  G06F13/38

Abstract: An intergrated circuit (IC) chip includes receiver circuitry to receive signals from a second IC chip. The receiver circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate at least one tap weight corresponding to the at least one tap based on edge information of previously received signals.

公开(公告)号：US20220345155A1

公开(公告)日：2022-10-27

申请号：US17744311

申请日：2022-05-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03M13/05 ,  G06F13/16 ,  G06F3/06 ,  G06F11/10

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

公开(公告)号：US20220337232A1

公开(公告)日：2022-10-20

申请号：US17668584

申请日：2022-02-10

Applicant: Rambus Inc.

Inventor： Charles Walter BOECKER ,  Roxanne VU ,  Eric Douglas GROEN

IPC: H03K5/13 ,  H03K3/356 ,  H03K5/135

Abstract: Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

公开(公告)号：US20220334738A1

公开(公告)日：2022-10-20

申请号：US17721176

申请日：2022-04-14

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent Steven Haukness

IPC: G06F3/06

Abstract: A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

公开(公告)号：US11476868B2

公开(公告)日：2022-10-18

申请号：US17153157

申请日：2021-01-20

Applicant: RAMBUS INC.

Inventor： Shankar Tangirala

IPC: H03M1/36 ,  H03M1/46

Abstract: A dual-loop analog to digital converter (ADC) includes an asynchronous inner loop including first and second comparators and a state machine, where outputs of the first and second comparators are coupled to inputs of the state machine, and where outputs of the state machine are cross-coupled to enable ports of the first and second comparators. The ADC includes a synchronous outer loop including a successive approximation register (SAR), a digital to analog converter (DAC), and the first and second comparators, where the outputs of the first and second comparators are coupled to inputs of the SAR, an N-bit output of the SAR is coupled to an N-bit input of the DAC, and a differential output of the DAC is coupled to inputs of the first and second comparators, where a state of the state machine is independent of the state of the SAR.