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公开(公告)号：US20240257863A1
公开(公告)日：2024-08-01
申请号：US18584371
申请日：2024-02-22
申请人： Rambus Inc.
发明人： Frederick A. Ware , Ely K. Tsern , John E. Linstadt , Thomas A. Giovannini , Scott C. Best , Kenneth L. Wright
IPC分类号： G11C11/4093 , G11C5/02 , G11C5/06 , G11C7/10 , G11C8/12 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C29/00 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/18
CPC分类号： G11C11/4093 , G11C5/025 , G11C5/063 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C29/824 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , G11C7/10 , G11C7/1012 , G11C7/1066 , G11C7/1093 , G11C8/12 , H01L24/16 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/06135 , H01L2224/06136 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181
摘要： A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
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公开(公告)号：US20240004813A1
公开(公告)日：2024-01-04
申请号：US18130355
申请日：2023-04-03
申请人： Rambus Inc.
CPC分类号： G06F13/1684 , G06F11/073 , G06F13/4027 , G06F11/0751 , G06F11/0784 , Y02D10/00 , G06F11/0772 , G06F11/2007 , G06F11/1658 , G06F11/1044 , G06F11/1048 , G06F11/079
摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
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公开(公告)号：US11862236B1
公开(公告)日：2024-01-02
申请号：US17588561
申请日：2022-01-31
申请人： Rambus Inc.
IPC分类号： G11C7/10 , G11C11/4093 , G11C11/4076 , G06F12/14 , G06F13/16 , G11C11/4072 , G11C11/408 , G11C29/38 , G11C29/32 , G11C29/22 , G11C11/4091 , G11C5/04
CPC分类号： G11C11/4093 , G06F12/1433 , G06F13/1673 , G06F13/1678 , G11C7/1072 , G11C11/408 , G11C11/4072 , G11C11/4076 , G11C11/4091 , G11C29/22 , G11C29/32 , G11C29/38 , G06F2212/1052 , G11C5/04 , Y02D10/00
摘要： In a memory component programmed to operate in a first operating mode and having a page buffer and a fixed-width data interface, N bits of a command/address value are decoded to access one of 2N columns of data within the page-buffer, with that column of data output via the fixed-width data interface over a first burst interval. If programmed to operate in a second operating mode, M bits of the command/address value are decoded to access a larger column of data—one of 2M columns of data within the page buffer, where M
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公开(公告)号：US11836099B2
公开(公告)日：2023-12-05
申请号：US17548510
申请日：2021-12-11
申请人： Rambus Inc.
IPC分类号： G06F13/16 , G06F12/0868 , G06F12/0888 , G11C7/10 , G06F3/06 , G06F11/10 , G06F12/0895 , G06F13/28 , G11C29/52
CPC分类号： G06F13/1678 , G06F3/0604 , G06F3/0613 , G06F3/0619 , G06F3/0634 , G06F3/0656 , G06F3/0673 , G06F11/1004 , G06F11/1068 , G06F12/0868 , G06F12/0888 , G06F12/0895 , G06F13/28 , G11C7/10 , G11C29/52 , G06F2212/1016 , G06F2212/1032 , G06F2212/403
摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.
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公开(公告)号：US11815940B2
公开(公告)日：2023-11-14
申请号：US17748762
申请日：2022-05-19
申请人： Rambus Inc.
CPC分类号： G06F13/287 , G06F13/16 , G11C5/04 , G11C7/10 , G11C7/1045 , G06F2213/28
摘要： The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
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公开(公告)号：US11705187B2
公开(公告)日：2023-07-18
申请号：US17501311
申请日：2021-10-14
申请人： Rambus Inc.
IPC分类号： G11C7/10 , G11C11/4093 , G11C11/4096 , G06F11/10 , G11C7/02 , G11C29/52 , G11C29/04
CPC分类号： G11C11/4093 , G06F11/1048 , G11C7/02 , G11C11/4096 , G11C29/52 , G11C2029/0411
摘要： Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
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公开(公告)号：US20220101912A1
公开(公告)日：2022-03-31
申请号：US17501311
申请日：2021-10-14
申请人： Rambus Inc.
IPC分类号： G11C11/4093 , G11C11/4096 , G06F11/10 , G11C7/02 , G11C29/52
摘要： Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
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公开(公告)号：US11264085B1
公开(公告)日：2022-03-01
申请号：US16927892
申请日：2020-07-13
申请人： Rambus Inc.
IPC分类号： G11C11/4093 , G06F13/16 , G11C11/4076 , G11C11/4091 , G06F12/14 , G11C11/408 , G11C11/4072 , G11C29/38 , G11C29/32 , G11C29/22 , G11C7/10 , G11C5/04
摘要： In a memory component having a page buffer with 2N independently accessible regions, N bits of a command/address value are decoded to access contents within a first one of the 2N page-buffer regions if a configuration value specifies a first addressing resolution and, if the configuration value specifies a second addressing resolution, a composite address that includes fewer than N bits of the command/address value together with a plurality of bits generated within the memory component to access contents within a second one of the 2N page-buffer regions.
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9.发明申请公开(公告)号：US20190266115A1
公开(公告)日：2019-08-29
申请号：US16290375
申请日：2019-03-01
申请人： Rambus Inc.
摘要： The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
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公开(公告)号：US10339999B2
公开(公告)日：2019-07-02
申请号：US16011539
申请日：2018-06-18
申请人： Rambus Inc.
IPC分类号： G11C7/10 , G11C11/4093 , G11C11/4096 , G06F11/10 , G11C7/02 , G11C29/52 , G11C29/04
摘要： Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
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