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公开(公告)号：US11132147B2
公开(公告)日：2021-09-28
申请号：US16579095
申请日：2019-09-23
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
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公开(公告)号：US20210157494A1
公开(公告)日：2021-05-27
申请号：US17090630
申请日：2020-11-05
Applicant: Micron Technology, Inc.
Inventor： Scott E. Schaefer , Aaron P. Boehm
IPC: G06F3/06
Abstract: Methods, systems, and devices for refresh counters in a memory system are described. In some examples, a memory device may include two or more counters configured to increment a respective count based on refresh operations performed on a memory array. A comparison may be made between two or more of the respective counts, which may include determining a difference between the respective counts or a difference in rate of incrementing. A memory device may transmit an indication to a host device based on determining a difference between counters, and the memory device, the host device, or both, may perform various operations or enter various operational modes based on the determined difference.
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公开(公告)号：US20210152994A1
公开(公告)日：2021-05-20
申请号：US17160973
申请日：2021-01-28
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm
IPC: H04W4/44 , G06F15/173 , H04L29/08 , H04B1/38
Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources on vehicles or base stations are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a wireless base station coupled to a first processor coupled to a first memory resource that are configured to enable formation of a memory pool to share data between the first memory resource and a second memory resource at a vehicle responsive to a request to access the second memory resource from the first processor transmitted via the base station. The data shared by the second memory resource is determined to enable performance of a particular functionality, stored by the first memory resource, as at least part of a mission profile for transit of the vehicle.
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公开(公告)号：US20210149569A1
公开(公告)日：2021-05-20
申请号：US17157797
申请日：2021-01-25
Applicant: Micron Technology, Inc.
Inventor： Erika Prosser , Aaron P. Boehm , Debra M. Bell
Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.
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公开(公告)号：US10936209B2
公开(公告)日：2021-03-02
申请号：US16433848
申请日：2019-06-06
Applicant: Micron Technology, Inc.
Inventor： Erika Prosser , Aaron P. Boehm , Debra M. Bell
Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.
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Patent Agency Ranking
公开(公告)号：US10908876B2
公开(公告)日：2021-02-02
申请号：US16553247
申请日：2019-08-28
Applicant: Micron Technology, Inc.
Inventor： Aaron P. Boehm
IPC: G06F11/00 , G06F7/20 , G06F1/30 , H03K19/173 , G06F3/06
Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.
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公开(公告)号：US20210026644A1
公开(公告)日：2021-01-28
申请号：US17065749
申请日：2020-10-08
Applicant: Micron Technology, Inc.
Inventor： Glen E. Hush , Aaron P. Boehm , Fa-Long Luo
Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
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公开(公告)号：US10818359B2
公开(公告)日：2020-10-27
申请号：US16231224
申请日：2018-12-21
Applicant: Micron Technology, Inc.
Inventor： Glen E. Hush , Aaron P. Boehm , Fa-Long Luo
Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.
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公开(公告)号：US10785786B2
公开(公告)日：2020-09-22
申请号：US16142025
申请日：2018-09-26
Applicant: Micron Technology, Inc.
Inventor： Fa-Long Luo , Glen E. Hush , Aaron P. Boehm
Abstract: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).
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公开(公告)号：US10779145B2
公开(公告)日：2020-09-15
申请号：US16142013
申请日：2018-09-26
Applicant: Micron Technology, Inc.
Inventor： Fa-Long Luo , Glen E. Hush , Aaron P. Boehm
IPC: G06F3/06 , H04W4/70 , H04W72/04 , H04W72/12 , H04W74/02 , H04W74/04 , H04W74/08 , H04W88/06 , H04W92/18
Abstract: Methods, apparatuses, and systems related to wireless main memory for computing are described. A device may include a processor that is wirelessly coupled to a memory array, which may be in a physically separate device. The processor may execute instructions stored in and wirelessly communicated from the memory array. The processor may read data from or write data to the memory array via a wireless communication link (e.g., using resources of an ultra high frequency, super high frequency, and/or extremely high frequency band). Several devices may have a small amount of local memory (or no local memory) and may share, via a wireless communication link, a main memory array. Memory devices may include memory resources and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).
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