公开(公告)号：US20180061481A1

公开(公告)日：2018-03-01

申请号：US15664140

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4094 ,  H01L27/108

CPC classification number: G11C11/4097 ,  G11C7/02 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  H01L27/108

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

公开(公告)号：US20180061460A1

公开(公告)日：2018-03-01

申请号：US15667234

申请日：2017-08-02

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C7/067 ,  G11C2207/063 ,  H01L21/8221 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10897 ,  H01L29/66666

Abstract: A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor is included and a fourth p-type transistor is above the third p-type transistor. A lower voltage activation line is electrically coupled to n-type source/drain regions that are elevationally between respective gates of the first and second n-type transistors. A higher voltage activation line is electrically coupled to p-type source/drain regions that are elevationally between respective gates of the third and fourth p-type transistors.

公开(公告)号：US20170358338A1

公开(公告)日：2017-12-14

申请号：US15181188

申请日：2016-06-13

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/22 ,  G11C11/4099 ,  G11C7/14

CPC classification number: G11C11/2273 ,  G11C7/14 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/4099 ,  G11C2211/5634

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which a subset of the memory cells is designated as reference memory cells. Each reference memory cell may be paired to an active memory cell and may act as a reference signal when sensing the active memory cell. Each pair of active and reference memory cells may be connected to a single access line. Sense components (e.g., sense amplifiers) associated with reference memory cells may be deactivated in half density mode. The entire memory array may be operated in half density mode, or a portion of the array may operate in half density mode and the remainder of the array may operate in full density mode.

公开(公告)号：US20150117124A1

公开(公告)日：2015-04-30

申请号：US14068940

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Howard Kirsch ,  Tae H. Kim

IPC: G11C7/08 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/12

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有第一数据线，第二数据线，第一晶体管，读出放大器和电路的装置和方法。 在从与第一数据线相关联的存储器单元获得信息的操作的第一阶段期间，第一晶体管可以操作以将第一数据线耦合到第一节点。 第二晶体管可以在第一阶段期间将第二数据线耦合到第二节点。 电路可操作以在操作期间将第一信号施加到第一晶体管的栅极，并且在操作期间将第二信号施加到第二晶体管的栅极。 感测放大器可以在操作的第二阶段期间操作以在第一和第二数据线上执行感测功能。 描述附加的装置和方法。