公开(公告)号：US20050265103A1

公开(公告)日：2005-12-01

申请号：US10982277

申请日：2004-11-05

Applicant: Perry Remaklus ,  Robert Walker

Inventor： Perry Remaklus ,  Robert Walker

IPC: G11C11/406 ,  G11C7/00

CPC classification number: G11C11/40611 ,  G11C11/406

Abstract: A memory system is provided. The system includes a volatile memory having a number of banks and configured to engage in one of a number of operating modes including an auto-refresh mode and a self-refresh mode, and a memory controller configured to direct the volatile memory to engage in one of the operating modes. Upon the memory controller directing the volatile memory to engage in the self-refresh mode, the memory controller is further configured to provide an entry bank address to the volatile memory, the entry bank address corresponding to the first bank that is to be refreshed during the self-refresh mode. Upon the volatile memory exiting the self-refresh mode, the volatile memory is further configured to make an exit bank address available to the memory controller, the exit bank address corresponding to the last bank that was refreshed prior to the volatile memory exiting the self-refresh mode.

Abstract translation: 提供了一种存储系统。 该系统包括具有多个存储体并被配置为参与包括自动刷新模式和自刷新模式的多种操作模式中的一种操作模式的易失性存储器，以及配置为引导易失性存储器参与一个 的操作模式。 在存储器控制器引导易失性存储器进行自刷新模式的情况下，存储器控制器还被配置为向易失性存储器提供入口库地址，对应于将在第 自刷新模式。 在易失性存储器退出自刷新模式时，易失性存储器被进一步配置为使存储器控制器可用的出库组地址，对应于在易失性存储器离开自组织之前刷新的最后一个存储体的出库组地址， 刷新模式。

公开(公告)号：US20050232541A1

公开(公告)日：2005-10-20

申请号：US11104545

申请日：2005-04-13

Applicant: Stephen Mihailov ,  Dan Grobnic ,  Christopher Smelser ,  Robert Walker ,  Ping Lu ,  Huimin Ding ,  George Henderson ,  Xiaoli Dai

Inventor： Stephen Mihailov ,  Dan Grobnic ,  Christopher Smelser ,  Robert Walker ,  Ping Lu ,  Huimin Ding ,  George Henderson ,  Xiaoli Dai

IPC: G02B6/02 ,  G02B6/34

CPC classification number: G02B6/021 ,  G02B6/02133 ,  G02B6/02142 ,  G02B6/02147

Abstract: A retro-reflective sensor for sensing mechanical, chemical or temperature related information, is disclosed. The sensor is formed of an optical waveguide suitable for use in-situ in a high temperature environment having a Bragg grating written into a core region thereof with short-pulsed electromagnetic radiation, said optical waveguide having a glass transition temperature substantially higher than that of silica. Preferably the sensor is written into a length of sapphire fiber or within a zirconium waveguide. Preferably the pulse duration of the short pulsed electromagnetic radiation is less than 500 picoseconds.

Abstract translation: 公开了一种用于感测机械，化学或温度相关信息的回射传感器。 传感器由适合在高温环境中原位使用的光波导形成，其中布拉格光栅用短脉冲电磁辐射写入其核心区域，所述光波导的玻璃化转变温度明显高于二氧化硅 。 优选地，传感器被写入蓝宝石光纤的长度或在锆波导内。 优选地，短脉冲电磁辐射的脉冲持续时间小于500皮秒。

公开(公告)号：US20050174539A1

公开(公告)日：2005-08-11

申请号：US11032215

申请日：2005-01-11

Applicant: Robert Walker ,  Bradley Caruk

Inventor： Robert Walker ,  Bradley Caruk

IPC: G03B25/00 ,  G09F19/22

CPC classification number: G09F19/22 ,  G09F2019/221

Abstract: A system displays a collection of stationary images as a motion picture to passengers travelling in a vehicle along a pathway. In a first embodiment, the vehicle moves at a known speed and known distance from the images. The system includes an image illumination system including stroboscopic lighting for each image. The images, placed in parallel along the walls of the pathway of the vehicle, are adapted in number, size, and spacing for a vehicle travelling at the known speed and at the known distance from images on one or both sides of the vehicle such as to maintain an approximately constant viewing rate and perceived size of the images. Glare due to interior lighting in the vehicle is reduced or eliminated by selecting the appropriate illumination intensity for the stroboscopic lighting. In an alternate configuration, a speed sensor monitors speed of the vehicle to determine the appropriate cycling rate of the images. Also, the images themselves may be cycled intermittently with a blank image while remaining steadily illuminated.

Abstract translation: 系统将沿车道行驶的乘客的静止图像集合显示为运动图像。 在第一实施例中，车辆以已知的速度和已知距离的图像移动。 该系统包括一个包括每个图像的频闪照明的图像照明系统。 沿着车辆的路径的壁平行放置的图像适用于以已知速度行驶的车辆的数量，尺寸和间隔，并且距离车辆的一侧或两侧上的图像已知距离，例如 以保持近似恒定的观看速率和感觉到的图像大小。 通过为频闪照明选择适当的照明强度来减少或消除车辆内部照明引起的眩光。 在替代配置中，速度传感器监测车辆的速度以确定图像的适当循环速率。 此外，图像本身可以与空白图像间歇地循环，同时保持稳定地照亮。

公开(公告)号：US20050160390A1

公开(公告)日：2005-07-21

申请号：US10707845

申请日：2004-01-16

Applicant: Henry Bonges ,  Michael Gray ,  Jason Hibbeler ,  Kevin McCullen ,  Robert Walker

Inventor： Henry Bonges ,  Michael Gray ,  Jason Hibbeler ,  Kevin McCullen ,  Robert Walker

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

Abstract translation: 用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。 本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。 联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

公开(公告)号：US20050147351A1

公开(公告)日：2005-07-07

申请号：US11005696

申请日：2004-12-06

Applicant: Robert Johnstone ,  Royston Powell ,  Robert Griffin ,  Robert Walker ,  Brian Buck

Inventor： Robert Johnstone ,  Royston Powell ,  Robert Griffin ,  Robert Walker ,  Brian Buck

IPC: G02F1/035 ,  G02F1/225 ,  G02F1/313

CPC classification number: G02F1/3133

Abstract: An optical modulator comprises first and second optical waveguides having first and second electrodes respectively associated therewith, and an electrically conductive region associated with both waveguides. The electrodes have inputs for an electrical signal at input ends thereof, and outputs for the electrical signal at opposite output ends thereof. The conductive region is electrically connected to the output ends of the first and second electrodes such that an electric field created by the electrical signal between the first electrode and the conductive region is substantially equal in magnitude to an electric field created by the electrical signal between the second electrode and the conductive region. The balancing of the electric fields experienced by the waveguides enables the modulation of light in the two waveguides to be balanced. The modulator may be a Mach-Zehnder modulator, and the balanced modulation may result in amplitude modulation of the optical output of the modulator, generally without phase modulation.

Abstract translation: 光调制器包括具有分别与其相关联的第一和第二电极的第一和第二光波导以及与两个波导相关联的导电区域。 电极在其输入端具有用于电信号的输入，并且在其相对的输出端输出电信号。 导电区域电连接到第一和第二电极的输出端，使得由第一电极和导电区域之间的电信号产生的电场在幅度上基本上等于由电信号产生的电场 第二电极和导电区域。 波导经历的电场的平衡使得能够平衡两个波导中的光的调制。 调制器可以是马赫 - 策德尔（Mach-Zehnder）调制器，并且平衡调制可以导致调制器的光输出的幅度调制，通常没有相位调制。

公开(公告)号：US20050125748A1

公开(公告)日：2005-06-09

申请号：US10707287

申请日：2003-12-03

Applicant: Michael Gray ,  Kevin McCullen ,  Gustavo Tellez ,  Robert Walker

Inventor： Michael Gray ,  Kevin McCullen ,  Gustavo Tellez ,  Robert Walker

IPC: G06F17/50 ,  H01L21/82

CPC classification number: G06F17/5068

Abstract: A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

Abstract translation: 一种方法，系统和程序产品，其以基本规则和用户意图的形式实现电路设计的区域最小化，同时遵守显式和隐式设计约束。 最长路径算法用于生成比例因子。 缩放因子用于将电路设计的尺寸减小到最小法律尺寸。 缩放可能之后是应用minpert分析来校正由缩放引入的任何错误。 所产生的设计缩小（或扩展），所有元素都通过相同的因素一起缩减（或增长），并保持元素的相对关系。 此外，本发明在存在正循环的情况下是可操作的，可以用缩放来运行，其结冰或冻结规则的尺寸，并且可以应用于技术迁移。

公开(公告)号：US20050122239A1

公开(公告)日：2005-06-09

申请号：US10730443

申请日：2003-12-08

Applicant: Robert Walker

Inventor： Robert Walker

IPC: H03M5/02 ,  H03M5/04 ,  H04L25/02 ,  H04L25/49

CPC classification number: H04L25/028 ,  H03M5/04 ,  H04L25/4917

Abstract: A chip to chip interface comprises a driver configured to receive a data signal and provide an output signal at a first level in response to receiving an odd number of consecutive logic highs in the data signal, at a second level in response to receiving an odd number of consecutive logic lows in the data signal, at a third level in response to receiving an even number of consecutive logic highs in the data signal and at a fourth level in response to receiving an even number of consecutive logic lows in the data signal.

Abstract translation: 芯片到芯片接口包括驱动器，其被配置为接收数据信号并响应于在第二电平响应于接收奇数而在第二电平上接收奇数个数据信号中的连续逻辑高电平而提供第一电平的输出信号 响应于在数据信号中接收到偶数个连续的逻辑高电平并且响应于在数据信号中接收到偶数个连续的逻辑低电平而在第四电平处在数据信号中的连续逻辑低电平。

公开(公告)号：US5933386A

公开(公告)日：1999-08-03

申请号：US997509

申请日：1997-12-23

Applicant: Robert Walker ,  Stephen Camacho ,  Tim Lao

Inventor： Robert Walker ,  Stephen Camacho ,  Tim Lao

IPC: G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C5/145 ,  G11C7/12

Abstract: An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.

Abstract translation: 公开了一种用于驱动存储器阵列的位线驱动器的装置。 存储器阵列具有行线，由位线驱动器驱动的互补的位线对，以及位线和行线的交点处的存储器单元。 第一和第二互补写入数据线提供一些要写入驱动器和位的补码。 升压电压的源极耦合到电平移位器，当写使能线和第一写数据线被断言时，电平转换器将升压电压传导到位线驱动器。 当写使能线被断言时，数据位通过双稳态锁存器锁存到位线驱动器。 驱动存储器阵列的位线的方法包括接收要写入位线的数据位和数据位的补码; 将一个数据位升高到大于存储器阵列的电源电压的电压; 并将数据位驱动到位线驱动器。

公开(公告)号：US5903466A

公开(公告)日：1999-05-11

申请号：US581379

申请日：1995-12-29

Applicant: James Beausang ,  Chris Ellingham ,  Robert Walker

Inventor： James Beausang ,  Chris Ellingham ,  Robert Walker

IPC: G01R31/317 ,  G01R31/3185 ,  G06F17/50 ,  G06F17/00

CPC classification number: G01R31/31704 ,  G01R31/31716 ,  G01R31/318586 ,  G06F17/5045 ,  G06F2217/14

Abstract: A computer implemented process and system for providing a scan insertion process having a reduced set of constraint driven compiler optimizations that provide an efficient and effective optimization for design for test implementations. The present invention includes a three tiered effort performance optimization process within a scan insertion process; a first tier operates to perform a set of optimizations (size design) only on elements of the design added for design for test (DFT). The second tier offers the first tier and performs the size design optimizations across all of the design while the third tier offers the second tier with sequential optimizations, circuit size downs, and another size design. Each higher user-selectable tier offers more complex optimizations and consumes additional processing time. An option to perform design constraints optimization (max fanout, max signal transition, and max capacitance) is also available. By utilizing a reduced set of performance optimizations, the present invention offers a post scan insertion compile technique that is fast enough to be practically used on chip level netlists. Hierarchical compilations for DFT are therefore allowed. Since the modified scan insertion procedure can operate in conjunction with a TR compiler of the present invention, the modified scan insertion procedure breaks loopback connections and generates proper scan chains. The scan insertion process of the present invention is compatible with netlists that contain a mixture of scan cells and non-scan cells.

Abstract translation: 一种计算机实现的过程和系统，用于提供扫描插入过程，该过程具有减少的约束驱动编译器优化集合，其为测试实现的设计提供有效且有效的优化。 本发明包括在扫描插入过程中的三层努力性能优化过程; 第一层仅针对为测试设计（DFT）添加的设计元素执行一组优化（尺寸设计）。 第二层提供第一层，并在所有设计中执行尺寸设计优化，而第三层则提供了具有顺序优化，电路尺寸下降和另一种尺寸设计的第二层。 每个较高的用户可选层提供更复杂的优化，并消耗额外的处理时间。 还可以选择执行设计约束优化（最大扇出，最大信号转换和最大电容）。 通过利用一组减少的性能优化，本发明提供了一种足够快速地在芯片级网表上实际使用的扫描后插入编译技术。 因此允许DFT的分层编译。 由于修改的扫描插入过程可以与本发明的TR编译器一起操作，所以修改的扫描插入过程中断环回连接并产生适当的扫描链。 本发明的扫描插入过程与包含扫描单元和非扫描单元的混合物的网表相兼容。

公开(公告)号：US5703789A

公开(公告)日：1997-12-30

申请号：US581187

申请日：1995-12-29

Applicant: James Beausang ,  Robert Walker

Inventor： James Beausang ,  Robert Walker

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50

CPC classification number: G01R31/318583 ,  G01R31/31716 ,  G01R31/318342 ,  G01R31/318364 ,  G01R31/318378 ,  G01R31/318536 ,  G01R31/318572

Abstract: A computer implemented process and system for providing a test ready (TR) compiler with specific information regarding the impact of added scannable cells and resources on its mission mode design. In so doing, the TR compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the mission mode design are maintained. The TR compiler translates generic sequential cells into technology dependent non-scan cells. In the TR compiler, during replacement, scannable memory cells are used in place of these non-scan memory cells specified within the mission mode circuitry. In this way, the TR compiler is informed of the characteristics of the scannable memory cells during optimization. For test, the scannable memory cells are chained to each other to form chain chains of sequential cells. To account for chaining during compile, the TR compiler provides output driven loopback connections to simulate electrical characteristics of the chain during compile. In the above implementation, the TR compiler can efficiently provide translation of an HDL description with test implementations into a gate level netlist. With the addition of certain information regarding the test implementation (e.g., scan replacement is done and loopback connections are added), the TR compiler of the present invention can better optimize the overall layout for the addition of the test resources.

Abstract translation: 一种计算机实现的过程和系统，用于向测试就绪（TR）编译器提供关于附加的可扫描单元和资源对其任务模式设计的影响的具体信息。 这样做，TR编译器可以更有效地优化添加的测试资源（例如，可扫描单元和其他扫描路由资源），以便维护任务模式设计的预定性能和设计相关约束。 TR编译器将通用顺序单元转换为依赖于技术的非扫描单元。 在TR编译器中，在替换期间，可以使用可扫描存储单元代替任务模式电路中指定的这些非扫描存储单元。 以这种方式，在优化过程中，向TR编译器通知可扫描存储单元的特性。 为了测试，可扫描的记忆细胞彼此链接以形成顺序细胞的链。 为了在编译期间考虑链接，TR编译器提供输出驱动的环回连接，以在编译期间模拟链的电气特性。 在上述实现中，TR编译器可以有效地将HDL描述与测试实现一起翻译成门级网表。 通过添加关于测试实现的某些信息（例如，扫描更换完成并且添加了环回连接），本发明的TR编译器可以更好地优化用于添加测试资源的总体布局。