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    CLONED AND ORIGINAL CIRCUIT SHAPE MERGING
    1.
    发明申请
    CLONED AND ORIGINAL CIRCUIT SHAPE MERGING 失效
    克隆和原始电路形状合并

    公开(公告)号：US20050160390A1

    公开(公告)日：2005-07-21

    申请号：US10707845

    申请日：2004-01-16

    申请人： Henry Bonges ,  Michael Gray ,  Jason Hibbeler ,  Kevin McCullen ,  Robert Walker

    发明人： Henry Bonges ,  Michael Gray ,  Jason Hibbeler ,  Kevin McCullen ,  Robert Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

    摘要翻译： 用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。 本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。 联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

    INTEGRATED CIRCUIT SELECTIVE SCALING
    7.
    发明申请
    INTEGRATED CIRCUIT SELECTIVE SCALING 有权
    集成电路选择性缩放

    公开(公告)号：US20060085768A1

    公开(公告)日：2006-04-20

    申请号：US10711959

    申请日：2004-10-15

    申请人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    发明人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

    摘要翻译： 公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

    INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS
    9.
    发明申请
    INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS 有权
    使用VORONOI DIAGRAMS的集成电路增益

    公开(公告)号：US20060150130A1

    公开(公告)日：2006-07-06

    申请号：US10709292

    申请日：2004-04-27

    申请人： Robert Allen ,  Michael Gray ,  Jason Hibbeler ,  Mervyn Tan ,  Robert Walker

    发明人： Robert Allen ,  Michael Gray ,  Jason Hibbeler ,  Mervyn Tan ,  Robert Walker

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5081

    摘要： A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.

    摘要翻译： 一种在集成电路设计中计算临界面积的方法，所述方法包括：输入集成电路设计; 将变量与所述集成电路设计中的边缘的位置相关联; 以及将所述变量的成本函数与所述集成电路设计中的所述边缘之间的间隔相关联; 其中当所述集成电路设计中的所述边缘的位置和长度改变时，所述成本函数计算临界面积贡献，并且其中所述临界区域贡献包括所述集成电路设计中所述边缘之间的所述间隔的电气故障特征的量度。

    CIRCUIT AREA MINIMIZATION USING SCALING
    10.
    发明申请
    CIRCUIT AREA MINIMIZATION USING SCALING 失效
    使用缩放的电路面积最小化

    公开(公告)号：US20050125748A1

    公开(公告)日：2005-06-09

    申请号：US10707287

    申请日：2003-12-03

    申请人： Michael Gray ,  Kevin McCullen ,  Gustavo Tellez ,  Robert Walker

    发明人： Michael Gray ,  Kevin McCullen ,  Gustavo Tellez ,  Robert Walker

    IPC分类号： G06F17/50 ,  H01L21/82

    CPC分类号： G06F17/5068

    摘要： A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

    摘要翻译： 一种方法，系统和程序产品，其以基本规则和用户意图的形式实现电路设计的区域最小化，同时遵守显式和隐式设计约束。 最长路径算法用于生成比例因子。 缩放因子用于将电路设计的尺寸减小到最小法律尺寸。 缩放可能之后是应用minpert分析来校正由缩放引入的任何错误。 所产生的设计缩小（或扩展），所有元素都通过相同的因素一起缩减（或增长），并保持元素的相对关系。 此外，本发明在存在正循环的情况下是可操作的，可以用缩放来运行，其结冰或冻结规则的尺寸，并且可以应用于技术迁移。