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11 条记录 (耗时 0.025 秒)

    CLONED AND ORIGINAL CIRCUIT SHAPE MERGING
    1.
    发明申请
    CLONED AND ORIGINAL CIRCUIT SHAPE MERGING 失效
    克隆和原始电路形状合并

    公开(公告)号：US20050160390A1

    公开(公告)日：2005-07-21

    申请号：US10707845

    申请日：2004-01-16

    申请人： Henry Bonges ,  Michael Gray ,  Jason Hibbeler ,  Kevin McCullen ,  Robert Walker

    发明人： Henry Bonges ,  Michael Gray ,  Jason Hibbeler ,  Kevin McCullen ,  Robert Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

    摘要翻译： 用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。 本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。 联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

    INTEGRATED CIRCUIT SELECTIVE SCALING
    7.
    发明申请
    INTEGRATED CIRCUIT SELECTIVE SCALING 有权
    集成电路选择性缩放

    公开(公告)号：US20060085768A1

    公开(公告)日：2006-04-20

    申请号：US10711959

    申请日：2004-10-15

    申请人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    发明人： Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Stephen Runyon ,  Robert Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.

    摘要翻译： 公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。 在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。 本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

    CIRCUIT AREA MINIMIZATION USING SCALING
    8.
    发明申请
    CIRCUIT AREA MINIMIZATION USING SCALING 失效
    使用缩放的电路面积最小化

    公开(公告)号：US20050125748A1

    公开(公告)日：2005-06-09

    申请号：US10707287

    申请日：2003-12-03

    申请人： Michael Gray ,  Kevin McCullen ,  Gustavo Tellez ,  Robert Walker

    发明人： Michael Gray ,  Kevin McCullen ,  Gustavo Tellez ,  Robert Walker

    IPC分类号： G06F17/50 ,  H01L21/82

    CPC分类号： G06F17/5068

    摘要： A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

    摘要翻译： 一种方法，系统和程序产品，其以基本规则和用户意图的形式实现电路设计的区域最小化，同时遵守显式和隐式设计约束。 最长路径算法用于生成比例因子。 缩放因子用于将电路设计的尺寸减小到最小法律尺寸。 缩放可能之后是应用minpert分析来校正由缩放引入的任何错误。 所产生的设计缩小（或扩展），所有元素都通过相同的因素一起缩减（或增长），并保持元素的相对关系。 此外，本发明在存在正循环的情况下是可操作的，可以用缩放来运行，其结冰或冻结规则的尺寸，并且可以应用于技术迁移。

    VIA SPACING VIOLATION CORRECTION METHOD, SYSTEM AND PROGRAM PRODUCT
    9.
    发明申请
    VIA SPACING VIOLATION CORRECTION METHOD, SYSTEM AND PROGRAM PRODUCT 审中-公开
    通过空间暴露校正方法，系统和程序产品

    公开(公告)号：US20050240884A1

    公开(公告)日：2005-10-27

    申请号：US10709294

    申请日：2004-04-27

    申请人： Terry Frederick ,  Jason Hibbeler ,  Kevin McCullen ,  William Pokorny

    发明人： Terry Frederick ,  Jason Hibbeler ,  Kevin McCullen ,  William Pokorny

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method, system and program product for correcting via spacing violations by generating a redundant via to replace one of a pair of vias that violate a ground rule, are disclosed. The redundant via corrects the ground rule violation. The target via corresponding to the redundant via is then removed, which corrects the ground rule violation. The invention can be applied to any spacing ground rule including same net and different net rules, and may also be applied to a current technology or, during migration, to a new technology. The invention can be applied to different levels of a design to ensure ground rule compliance throughout the design.

    摘要翻译： 公开了一种用于通过产生冗余通道来更换间隔违规的方法，系统和程序产品，以替代违反基本规则的一对通孔中的一个。 冗余通道修正了基本规则违规。 然后删除对应于冗余通道的目标，这校正了违反基本规则的行为。 本发明可以应用于包括相同网络和不同网络规则的任何间隔地面规则，并且还可以应用于当前技术，或者在迁移期间应用于新技术。 本发明可以应用于不同级别的设计，以确保整个设计中的基本规则符合性。

    INTEGRATED CIRCUIT MACRO PLACING SYSTEM AND METHOD
    10.
    发明申请
    INTEGRATED CIRCUIT MACRO PLACING SYSTEM AND METHOD 失效
    集成电路宏放置系统及方法

    公开(公告)号：US20060026545A1

    公开(公告)日：2006-02-02

    申请号：US10710701

    申请日：2004-07-29

    申请人： Robert Allen ,  Steven Lovejoy ,  Kevin McCullen

    发明人： Robert Allen ,  Steven Lovejoy ,  Kevin McCullen

    IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455

    CPC分类号： G06F17/5072

    摘要： A method (300) of placing a to-be-placed integrated circuit macro (404) adjacent one or more already-placed macros (400) aboard an integrated circuit chip (100). The method includes the step of performing a canonical ordering of the edges of the to-be-placed and already placed macros. Then, an edge constraint vector (500, 526) is generated for each active edge (668) of the already-placed macro(s) and each edge of the to-be-placed macro. Each of the edge constraint vectors of the to-be-placed macro is compared to each edge constraint vector of the active edge(s) using a string matching algorithm so as to determine whether any edges of the to-be-placed macro are compatible with any active edges of the already-placed macro(s). The method may be implemented in a CAD system (600).

    摘要翻译： 将放置在集成电路芯片（100）上的一个或多个已经放置的宏（400）的待放置集成电路宏（404）放置的方法（300）。 该方法包括执行要放置的和已经放置的宏的边缘的规范排序的步骤。 然后，为已经放置的宏和待放置宏的每个边缘的每个活动边缘（668）生成边缘约束向量（500,526）。 使用字符串匹配算法将待放置的宏的每个边缘约束向量与活动边缘的每个边缘约束向量进行比较，以便确定要被放置的宏的任何边缘是否兼容 具有已放置宏的任何活动边。 该方法可以在CAD系统（600）中实现。