Gateway using resource directory
    141.
    发明授权

    公开(公告)号:US10542585B2

    公开(公告)日:2020-01-21

    申请号:US15716966

    申请日:2017-09-27

    Abstract: A system and method for allowing legacy devices to be discovered on a DotDot network is disclosed. The system includes a gateway device to interface between DotDot devices and legacy devices. In some embodiments, the gateway device has a plurality of network interfaces to communicate with these legacy devices. The gateway device discovers the legacy devices that it can communicate with. The gateway device then presents information about these legacy devices in a Resource Directory. In some embodiments, the Resource Directory is maintained within the gateway device. In other embodiments, the gateway device utilizes a Resource Directory that exists on the DotDot network.

    Adaptive jitter and spur adjustment for clock circuits

    公开(公告)号:US10511315B1

    公开(公告)日:2019-12-17

    申请号:US16138080

    申请日:2018-09-21

    Inventor: Vivek Sarda

    Abstract: An apparatus includes a control circuit configured to generate a frequency divider control signal approximating a fractional divide ratio. The apparatus includes a frequency divider configured to generate an output clock signal based on an input clock signal and an adjusted frequency divider control signal. The output clock signal is a frequency-divided version of the input clock signal. The apparatus includes a measurement circuit configured to provide digital time information corresponding to an edge of the output clock signal. The apparatus includes an adaptive adjustment circuit configured to generate the adjusted frequency divider control signal based on the frequency divider control signal and the digital time information.

    Slew-rate controlled supply voltage switching

    公开(公告)号:US10468983B2

    公开(公告)日:2019-11-05

    申请号:US14933285

    申请日:2015-11-05

    Abstract: An apparatus includes a slew rate regulation circuit, a plurality of switches and a controller circuit. The controller circuit controls the plurality of switches to decouple a first source supply voltage from a supply rail; control the plurality of switches to couple a second source supply voltage to the supply rail to replace the first source supply voltage with the second source supply voltage; and control the slew rate regulation circuit to regulate a slew rate of a voltage of the supply rail during a time interval in which the first source supply voltage is being replaced with the second source supply voltage.

    High output swing high voltage tolerant bus driver

    公开(公告)号:US10461964B1

    公开(公告)日:2019-10-29

    申请号:US16169757

    申请日:2018-10-24

    Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

    ECC memory controller to detect dangling pointers

    公开(公告)号:US10360104B2

    公开(公告)日:2019-07-23

    申请号:US15589217

    申请日:2017-05-08

    Inventor: Thomas S. David

    Abstract: A system and method of utilizing ECC memory to detect software errors and malicious activities is disclosed. In one embodiment, after a pool of memory is freed, every data word in that pool is modified to ensure that an ECC error will occur if any data word in that pool is read again. In another embodiment, the ECC memory controller is used to detect and prevent non-secure applications from accessing secure portions of memory.

    State retention circuit that retains data storage element state during power reduction mode

    公开(公告)号:US10340894B1

    公开(公告)日:2019-07-02

    申请号:US15963316

    申请日:2018-04-26

    Abstract: A state retention circuit for retaining the state of a data storage element during a power reduction mode including a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled from between first and second states before entering the power reduction mode so that the storage latch latches the state of the data storage element. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention transistor is overpowered when the retention node is pulled to the second state in which the retention inverter quickly turns off the retention transistor. When the retention node is toggled back to the first state, the retention inverter keeps the retention transistor turned on during the power reduction mode.

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