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公开(公告)号：US11088819B1
公开(公告)日：2021-08-10
申请号：US16836706
申请日：2020-03-31
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
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公开(公告)号：US20210157356A1
公开(公告)日：2021-05-27
申请号：US16693562
申请日：2019-11-25
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A system receives a first clock signal with a first frequency and a second clock signal having a second frequency lower than the first frequency. The system generates a new second clock signal aligned with the first clock signal based on a known phase/frequency relationship between the clock signals. A counter counts cycles of the first clock signal. The system generates a new second clock signal with an edge aligned with a first clock signal when the counter reaches a predetermined count value and the system resets the counter. A window opens that includes a time period when the edge of the first clock signal is expected. If an edge of the first clock signal is detected outside of the window, the counter is reset responsive to the detected edge.
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公开(公告)号：US10270457B2
公开(公告)日：2019-04-23
申请号：US15385311
申请日：2016-12-20
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage elements are coupled to the sigma delta modulator to store the divide values, M being at least 2. A selector circuit selects the respective divide values and supplies the divide values to a portion of an interpolative divider circuit, the portion including a divider and a phase interpolator. The interpolative divider generates an output clock signal having a first clock period that may be determined by the first and second divide values. The M storage elements are loaded by a clock signal that is slower than the output clock signal by at least half.
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4.发明授权公开(公告)号：US11088816B1
公开(公告)日：2021-08-10
申请号：US16836713
申请日：2020-03-31
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
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公开(公告)号：US10608647B1
公开(公告)日：2020-03-31
申请号：US16221188
申请日：2018-12-14
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Vivek Sarda
Abstract: A method includes generating first frequency metrics for a first received network clock signal using a local reference clock signal. The method includes, in response to the first received network clock signal being available and satisfying a quality metric, generating a network delay estimate using a first error estimate based on the first received network clock signal, and updating stored frequency metrics for the first received network clock signal with the first frequency metrics. The method includes generating an output clock signal based on received packets and the network delay estimate. The first frequency metrics for the first received network clock signal may include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.
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Patent Agency Ranking
公开(公告)号：US10520547B2
公开(公告)日：2019-12-31
申请号：US15720858
申请日：2017-09-29
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
IPC: G01R31/317 , G01R31/3185
Abstract: In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.
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公开(公告)号：US10483987B1
公开(公告)日：2019-11-19
申请号：US16221192
申请日：2018-12-14
Applicant: Silicon Laboratories Inc.
Inventor： Harihara Subramanian Ranganathan , Vivek Sarda
Abstract: A method for operating a clock product includes generating a quality determination for a reference clock signal based on frequency metrics for a plurality of independent clock signals. The frequency metrics are generated using the reference clock signal. The method includes generating an output clock signal by locking to an active clock signal selected from the plurality of independent clock signals in response to the quality determination satisfying a predetermined quality metric. For each input clock signal of the plurality of independent clock signals, the frequency metrics include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts, and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.
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公开(公告)号：US20190101590A1
公开(公告)日：2019-04-04
申请号：US15720858
申请日：2017-09-29
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
IPC: G01R31/317 , G01R31/3185
Abstract: In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.
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公开(公告)号：US20210157355A1
公开(公告)日：2021-05-27
申请号：US16693559
申请日：2019-11-25
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.
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公开(公告)号：US10712390B2
公开(公告)日：2020-07-14
申请号：US15713178
申请日：2017-09-22
Applicant: Silicon Laboratories Inc.
Inventor： Vivek Sarda
IPC: G01R31/3185 , G01R31/319 , G05F1/10
Abstract: During scan testing a voltage regulator is programmed to supply a first voltage to logic under test during a shift portion of the scan test, a second voltage during a first portion of a capture portion of the scan test and at least a third voltage during a second portion of the capture portion of the scan test. The availability of a programmable voltage regulator during shift and capture portions of scan testing allows a less stressful voltage to be used during a shift portion of the scan test to reduce shift failures and allows various voltages to be used during capture portions of the scan testing as a surrogate for testing at different temperatures and to provide more flexibility in testing margins.
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