公开(公告)号：US07268368B1

公开(公告)日：2007-09-11

申请号：US10651884

申请日：2003-08-29

Applicant: David J. Knapp

Inventor： David J. Knapp

IPC: H01L31/12

CPC classification number: H01L31/0203 ,  G02B6/4206 ,  G02B6/423 ,  H01L31/02325 ,  H01L2224/48247 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package and method for forming the same is disclosed herein. The semiconductor package includes a package support member, a pair of optoelectronic devices spaced from each other and coupled to the package support member, and an optically transmissive portion for separately encapsulating the pair of optoelectronic devices. A pair of lenses is formed as a unibody structure with the optically transmissive portion. The semiconductor package also includes an optically opaque portion, which extends between and around the separately encapsulated devices to optically isolate encapsulated optical devices. The optically opaque portion also extends outward from portions of the encapsulated devices, thereby forming a pair of fiber optic receptacles as a unibody structure with the optically opaque portion. By forming lensing elements and fiber optic receptacles in such a manner, the present method provides an easier and more accurate means by which to passively align optical conductors to underlying encapsulated optical devices.

Abstract translation: 本文公开了一种半导体封装及其形成方法。 半导体封装包括封装支撑构件，彼此间隔开并耦合到封装支撑构件的一对光电器件，以及用于单独封装该对光电器件的光学透射部分。 一对透镜形成为具有透光部分的一体结构。 半导体封装还包括光学不透明部分，其在单独封装的器件之间和周围延伸，以光学隔离封装的光学器件。 光学不透明部分也从封装装置的部分向外延伸，由此形成一对光纤插座，作为具有光不透明部分的一体结构。 通过以这种方式形成透镜元件和光纤插座，本方法提供了一种更容易和更精确的手段，通过该装置将光导体无源对准到底层封装光学器件。

公开(公告)号：US20070186020A1

公开(公告)日：2007-08-09

申请号：US11348219

申请日：2006-02-06

Applicant: Barry Drexler ,  Steven Sipek

Inventor： Barry Drexler ,  Steven Sipek

IPC: G06F13/368 ,  G06F13/00

CPC classification number: G06F13/368

Abstract: A system may comprise multiple master/slave devices coupled to a common bus, where one of the devices may operate as the current master device and the other devices may operate as current slave devices. Current slave devices may embed bus ownership request information within response packets transmitted in response to standard bus operations, such as reads and writes, issued by the current master device. When the current master device is idle, its bus interface may continually poll the current slave devices at regular intervals, according to a specified protocol, to ascertain whether any of them are requesting bus ownership. A response to a request for bus ownership received by the current master device may be configured according to desired system functionality. In one system, ownership may always be transferred to the requesting device. In other systems, the current master device may transmit a subsequent standard bus operation request packet, or a unique response packet, either comprising embedded information indicating whether ownership of the bus has been granted.

Abstract translation: 系统可以包括耦合到公共总线的多个主/从设备，其中一个设备可以作为当前主设备操作，并且其他设备可以作为当前从设备操作。 当前从设备可以将响应分组中的总线所有权请求信息嵌入到响应于由当前主设备发出的标准总线操作（例如读和写）。 当当前主设备空闲时，其总线接口可以按照规定的时间间隔连续轮询当前从设备，以确定其中任何一个是否请求总线所有权。 可以根据期望的系统功能来配置对当前主设备接收的对总线所有权请求的响应。 在一个系统中，所有权总是可以转移到请求设备。 在其他系统中，当前主设备可以发送随后的标准总线操作请求分组或独特的响应分组，其包括指示是否已经授权总线的所有权的嵌入信息。

公开(公告)号：US07193543B1

公开(公告)日：2007-03-20

申请号：US11219399

申请日：2005-09-02

Applicant: Scott C. McLeod ,  Kenneth W. Gay

Inventor： Scott C. McLeod ,  Kenneth W. Gay

IPC: H03M1/00

CPC classification number: G01K7/01 ,  H03K21/40 ,  H03M1/0827

Abstract: In one set of embodiments, a temperature measurement system may include an analog to digital converter (ADC) to produce digital temperature readings according to a difference base-emitter voltage (ΔVBE) developed across a PN-junction. A clock generating circuit may be configured to provide a sampling clock used by the ADC, which in some embodiments may be a delta-sigma ADC, in performing the conversions. The clock generating circuit may be configured to change the frequency of the sampling clock a specified number of times within each one of the one or more conversion cycles to reduce an error component in the temperature measurement, where the error component is produced by an interfering signal, such as an electromagnetic interference (EMI) signal being coherent with the sampling clock, and/or a noise residing on the voltage supply and also being coherent with the sampling clock.

Abstract translation: 在一组实施例中，温度测量系统可以包括模数转换器（ADC），以根据跨越PN结开发的差异基极 - 发射极电压（DeltaV + BE）来产生数字温度读数 。 时钟发生电路可以被配置为提供由ADC使用的采样时钟，ADC在一些实施例中可以是Δ-ΣADC来执行转换。 时钟发生电路可以被配置为在一个或多个转换周期的每一个周期内将采样时钟的频率改变指定次数，以减少温度测量中的误差分量，其中误差分量由干扰信号产生 ，例如与采样时钟相干的电磁干扰（EMI）信号和/或驻留在电压源上的噪声并且与采样时钟相干。

公开(公告)号：US07114019B2

公开(公告)日：2006-09-26

申请号：US09949288

申请日：2001-09-07

Applicant: Trenton B. Henry ,  Henry Wurzburg ,  Richard C. Counts ,  Christopher D. Sawran

Inventor： Trenton B. Henry ,  Henry Wurzburg ,  Richard C. Counts ,  Christopher D. Sawran

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: An interface chip is disclosed. In one embodiment, an interface chip includes a processor coupled to an internal data bus and an internal address bus. A plurality of interfaces, including at least on serial interface and at least one parallel interface are also coupled to the processor via the internal address bus and the internal data bus. The interface chip also includes data movement circuitry, wherein the data movement circuitry is configured for transmitting data between a first of the plurality of interfaces and a second of the plurality of interfaces using time division multiplexing.

公开(公告)号：US07106224B2

公开(公告)日：2006-09-12

申请号：US10218349

申请日：2002-08-14

Applicant: David J. Knapp ,  John G. Maddox ,  Joseph B. Gaalaas

Inventor： David J. Knapp ,  John G. Maddox ,  Joseph B. Gaalaas

IPC: H03M7/00

CPC classification number: H04J3/0647 ,  H04L7/0029

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source. However, sample rate conversion at the destination is preferred if the source sample rate is forwarded across the network relative to the frame transfer rate of the synchronous network. The sample rate converter simply produces a play rate from the transmitted information at the destination. Again, however, sample rate conversion compares relative phase difference changes similar to the phase difference compared in the digital PLL mode. As a further alternative, sample rates within the source and destination ports can be derived from the network frame rate using fractional dividers in the source and destination ports.

Abstract translation: 提供通信系统，通信系统的源和目的地端口和方法，用于以可能三种不同的方式之一传输数据。 数据以与采样率或源端口或目标端口内的主时钟相同或不同的帧采样率在网络上传输。 如果源端口的采样率是已知的，则可以使用目的端口内的PLL创建目标端口的采样率，并且仅在源端口中使用相位比较器。 相位比较器将网络传输速率和源采样率的相位或频率差转发到目的地端口，该目的端口然后生成等效于源的本地时钟，该时钟源以与之相同的速率进行播放的音频数据进行编译 在源头。 在经济上可行的情况下，采样率转换可以在源头使用。 然而，如果源采样率相对于同步网络的帧传输速率在网络上转发，则优选目的地的采样率转换。 采样率转换器简单地从目的地的发送信息产生播放速率。 然而，再次，采样率转换比较类似于在数字PLL模式下比较的相位差的相对相位差变化。 作为另一个替代方案，源端口和目的端口中的采样率可以使用源端口和目的端口中的分数分频器从网络帧速率导出。

公开(公告)号：US20060062339A1

公开(公告)日：2006-03-23

申请号：US10947891

申请日：2004-09-23

Applicant: Luis Briones

Inventor： Luis Briones

IPC: H03D3/24

CPC classification number: H03D13/003 ,  H04L7/033

Abstract: A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of the phase difference between the received data signal and a clock signal produced by a voltage-controlled oscillator (VCO) of the CDR circuit. The half-rate CDR typically changes the frequency of the clock signal and generates a clock signal that is aligned with the baud center of the received data signal. More specifically, when the half-rate CDR circuit is in a locked condition, both the rising and falling edges of the clock signal are aligned with the baud center of the received data signal. The half-rate CDR preferably generates a clock signal with an average frequency that is half the data rate of a received data signal.

Abstract translation: 用于恢复嵌入在接收数据信号中的时钟信息的线性半速率时钟和数据恢复（CDR）电路。 半速率CDR电路包括相位检测器，其可以接收数据信号并产生表示接收数据信号与由CDR电路的压控振荡器（VCO）产生的时钟信号之间的相位差的相位误差信号 。 半速率CDR通常改变时钟信号的频率并产生与接收的数据信号的波特中心对准的时钟信号。 更具体地，当半速率CDR电路处于锁定状态时，时钟信号的上升沿和下降沿均与接收数据信号的波特中心对准。 半速率CDR优选地生成具有接收数据信号的数据速率的一半的平均频率的时钟信号。

公开(公告)号：US20060039445A1

公开(公告)日：2006-02-23

申请号：US10924176

申请日：2004-08-23

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: G01K7/00

CPC classification number: G01K7/00 ,  G01K7/01

Abstract: A temperature measurement device may be implemented by coupling a PN-junction, which may be comprised in a diode, to an analog-to-digital converter (ADC) that comprises an integrator. Different currents may be successively applied to the diode, resulting in different VBE values across the diode. The ΔVBE values thus obtained may be successively integrated. Appropriate values for the different currents may be determined based on a set of mathematical equations, each equation relating the VBE value to the temperature of the diode, the current applied to the diode and parasitic series resistance associated with the diode. When the current sources with the appropriate values are sequentially applied to the diode and the resulting diode voltage differences are integrated by the integrator comprised in the ADC, the error in the temperature measurement caused by series resistance is canceled in the ADC, and an accurate temperature reading of the diode is obtained from the output of the ADC.

公开(公告)号：US20060020737A1

公开(公告)日：2006-01-26

申请号：US11223570

申请日：2005-09-09

Applicant: Piotr Szabelski

Inventor： Piotr Szabelski

IPC: G06F13/20

CPC classification number: G06F13/385

Abstract: A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to provide data received via the upstream port to each of the downstream data handlers. Accordingly, the upstream data handler is shared between the various downstream data handlers

Abstract translation: 设备可以包括上游端口和配置成以与上游端口不同的数据传输速率传输数据的多个下游端口。 该设备还可以包括几个下游数据处理器，每个下游数据处理器都耦合到相应的一个下行端口，以及耦合到上游端口的上游数据处理器。 数据处理程序被配置为实现USB协议。 上游数据处理器被配置为将经由上游端口接收的数据提供给每个下游数据处理程序。 因此，上游数据处理程序在各种下游数据处理程序之间共享

公开(公告)号：US20050256670A1

公开(公告)日：2005-11-17

申请号：US10843199

申请日：2004-05-11

Applicant: Leonid Bekker ,  Uri Segal

Inventor： Leonid Bekker ,  Uri Segal

IPC: G01P3/48 ,  G06F15/00

CPC classification number: G01P3/48

Abstract: A system and method for generating a test signal used in measuring the speed of a rotating device, such as a fan in a computer system is disclosed. A pulse width modulated (PWM) signal may power the fan with the duty cycle of the PWM signal controlling the speed of the fan. The fan may generate tachometer pulses used for monitoring RPM of the fan. The frequency of the test signal may be selected to be at least twice the frequency of the tachometer pulses. The test signal may be generated from a base frequency signal using two cascaded frequency dividers. The first divider may output a scaled base frequency signal obtained by dividing the base frequency signal by a user programmable scale frequency coefficient corresponding to a maximum test signal frequency for the fan. The second divider may output the test signal by dividing the scaled base frequency signal by a fraction frequency coefficient obtained from and proportional to the current PWM duty cycle value. The test signal may be multiplexed with the PWM signal to obtain existing tachometer pulses even when the PWM signal is not asserted. The scale frequency coefficient may only need to be programmed once for each fan.

Abstract translation: 公开了一种用于产生用于测量计算机系统中的诸如风扇之类的旋转装置的速度的测试信号的系统和方法。 脉宽调制（PWM）信号可以以控制风扇速度的PWM信号的占空比为风扇供电。 风扇可能会产生用于监控风扇转速的转速计脉冲。 测试信号的频率可以被选择为至少两倍于转速计脉冲的频率。 可以使用两个级联分频器从基频信号产生测试信号。 第一分频器可以输出通过将基频信号除以用于与风扇的最大测试信号频率相对应的用户可编程标度频率系数而获得的缩放基频信号。 第二分频器可以通过将经缩放的基本频率信号除以从当前PWM占空比值获得的分数频率系数并与其成比例地输出测试信号。 即使PWM信号未被置位，测试信号也可以与PWM信号进行多路复用以获得现有的转速计脉冲。 每个风扇只需要编程一次规模频率系数。

公开(公告)号：US06924709B2

公开(公告)日：2005-08-02

申请号：US10683621

申请日：2003-10-10

Applicant: Aniruddha Bashar

Inventor： Aniruddha Bashar

IPC: H03K3/011 ,  H03K3/0231 ,  H03B5/24

CPC classification number: H03K3/0231 ,  H03K3/011

Abstract: A system and method for designing an integrated relaxation oscillator that exhibits reduced change in the frequency of oscillation caused by process variation. Improved sensitivity to component variation due to process shift is achieved through using more than one structure type when implementing the resistors affecting the RC time constant and threshold (trip point) voltages of the oscillator. Structure types are related to the fabrication process and for a CMOS process include, but are not limited to n-diffusion, p-diffusion, n-well, p-well, pinched n-well, pinched p-well, poly-silicon and metal. Each structure type exhibits statistically independent process variations, allowing for application of Lyapunov's extension of the Central Limit Theorem for statistically uncorrelated events to desensitize the effect from different possible causes. Thus, improvement in the performance of the oscillator may be achieved with a reduced trim requirement and without using external precision resistors.