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151.发明授权Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and quadrature phase shift keying, and bit interleaving method using same 有权具有长度为64800，码率为3/15和正交相移键控的低密度奇偶校验码字的位交织器，以及使用相同的比特交织方法公开(公告)号：US09553696B2
公开(公告)日：2017-01-24
申请号：US14606958
申请日：2015-01-27
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , H03M13/1165 , H03M13/1177 , H03M13/17 , H03M13/255 , H03M13/2778 , H04L1/0041 , H04L1/0057 , H04L1/0071 , H04L1/0076
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为3/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于正交相移键控（QPSK）调制的调制器。
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152.发明授权Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same 有权具有长度为64800和码率为3/15和64符号映射的低密度奇偶校验码字的位交织器，以及使用相同位的比特交织方法公开(公告)号：US09553606B2
公开(公告)日：2017-01-24
申请号：US14625563
申请日：2015-02-18
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , G06F11/1076 , H03M13/1102 , H03M13/1151 , H03M13/1165 , H03M13/255 , H03M13/2739 , H03M13/2778 , H03M13/6552
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为64800且码率为3/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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153.发明授权Low density parity check encoder having length of 16200 and code rate of 5/15, and low density parity check encoding method using the same 有权长度为16200，码率为5/15的低密度奇偶校验编码器，以及使用该码的低密度奇偶校验编码方法公开(公告)号：US09479289B2
公开(公告)日：2016-10-25
申请号：US14496432
申请日：2014-09-25
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/255 , H03M13/036 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/616 , H04L1/0043 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为16200且码率为5/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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公开(公告)号：US12294637B2
公开(公告)日：2025-05-06
申请号：US17886167
申请日：2022-08-11
Inventor： Bo-Mi Lim , Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
IPC: H04L69/324 , H03M13/11 , H04L1/00
Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.
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公开(公告)号：US12155455B2
公开(公告)日：2024-11-26
申请号：US18146983
申请日：2022-12-27
Inventor： Sun-Hyoung Kwon , Sung-Ik Park , Nam-Ho Hur , Rufino Reydel Cabrera , Eneko Iradier , Jon Montalban , Pablo Angueira
IPC: H04H60/91
Abstract: Disclosed herein are a broadcast node and a method for dynamically managing radio resources and heterogeneous network connectivity. The broadcast node is installed for a transmitter of an intelligent broadcast/broadband network, wherein the broadcast node is configured to generate an attribute message including an associated identification parameter for connection to a broadcast core network, and initiate a series of communication protocols for connection with additional intelligent entities, and manage a service request queue, a radio resource, an interface, and one or more services.
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Patent Agency Ranking
公开(公告)号：US12074614B2
公开(公告)日：2024-08-27
申请号：US18330955
申请日：2023-06-07
Inventor： Sung-Ik Park , Heung-Mook Kim , Sun-Hyoung Kwon , Nam-Ho Hur
CPC classification number: H03M13/1157 , H03M13/1165 , H03M13/616 , H03M13/036 , H03M13/1185 , H03M13/2792 , H03M13/6552 , H04L1/0041 , H04L1/0043 , H04L1/0057 , H04L1/0058 , H04L1/0071
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US12047134B2
公开(公告)日：2024-07-23
申请号：US18049530
申请日：2022-10-25
Inventor： Hoi-Yoon Jung , Bo-Mi Lim , Sung-Ik Park , Hae-Chan Kwon , Sung-Jun Ahn , Nam-Ho Hur
IPC: H04B7/0456 , H03M13/25 , H04L1/00
CPC classification number: H04B7/0456 , H03M13/255 , H04L1/0071
Abstract: Disclosed herein are a broadcast signal transmission/reception method using multiple antennas and layered-division multiplexing and an apparatus for the same. A broadcast signal transmission apparatus includes a Multiple-Input Multiple-Output (MIMO) Bit-Interleaved Coded Modulation (BICM) unit for dividing enhanced layer data into two enhanced layer signals having different polarizations, a combination unit for generating a multiplexed signal corresponding to a first transmitting antenna by combining a core layer signal corresponding to core layer data with a first enhanced layer signal, and transmission signal generation units for generating a first transmission signal, corresponding to the multiplexed signal and transmitted through the first transmitting antenna, and a second transmission signal, corresponding to a second enhanced layer signal and transmitted through a second transmitting antenna.
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158.发明授权公开(公告)号：US12040928B2
公开(公告)日：2024-07-16
申请号：US18298498
申请日：2023-04-11
Inventor： Sung-Ik Park , Jae-Young Lee , Sun-Hyoung Kwon , Heung-Mook Kim
IPC: H04L27/26 , H04J11/00 , H04L1/00 , H04L7/08 , H04L65/611
CPC classification number: H04L27/2627 , H04J11/004 , H04L1/0041 , H04L1/0058 , H04L1/0068 , H04L1/0071 , H04L1/0072 , H04L7/08 , H04L27/26 , H04L27/2613 , H04L27/2647 , H04L65/611
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US11764808B2
公开(公告)日：2023-09-19
申请号：US17577280
申请日：2022-01-17
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/1165 , H03M13/1105 , H03M13/255 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0042 , H04L1/0071 , H04L27/3422 , H04L1/0057
Abstract: A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.
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公开(公告)号：US11750224B2
公开(公告)日：2023-09-05
申请号：US17165625
申请日：2021-02-02
Inventor： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
CPC classification number: H03M13/2792 , H03M13/036 , H03M13/116 , H03M13/1148 , H03M13/1165 , H03M13/255 , H03M13/616 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0071
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
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