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    Techniques for reducing accelerator-memory access costs in platforms with multiple memory channels
    152.
    发明授权
    Techniques for reducing accelerator-memory access costs in platforms with multiple memory channels 有权

    公开(公告)号：US10565133B2

    公开(公告)日：2020-02-18

    申请号：US15713001

    申请日：2017-09-22

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal

    IPC: G06F13/16 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0842 ,  G06F13/42

    Abstract: Methods and apparatus for reducing accelerator-memory access costs in platforms with multiple memory channels. The apparatus includes a computing platform having multiple accelerators and multiple memory devices accessed via a plurality of memory channels. Jobs are submitted via software running on the computing platform to access a function to be offloaded to an accelerator. Under the offloaded function, the accelerator accesses one or more buffers that collectively requiring access via multiple memory channels among the plurality of memory channels. Accelerators having an available instance of the function are identified, and an aggregate cost for accessing the one or more buffers via the multiple memory channels are calculated for each of the accelerators. The accelerator with the least aggregate cost is then selected to offload the function to. New Instruction Set Architecture (ISA) instructions are also disclosed to identify memory pages and memory channels used for buffers.

    Optimized selection of hash collision chains
    155.
    发明授权
    Optimized selection of hash collision chains 有权

    公开(公告)号：US10528539B2

    公开(公告)日：2020-01-07

    申请号：US15200556

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Daniel Cutter

    IPC: G06F17/30 ,  G06F16/22 ,  G06F16/2455 ,  G06F3/06

    Abstract: In an example, there is disclosed an apparatus, comprising: a data store comprising a hash table having for at least some rows a hash entry indexed by a hash value, and comprising a hash chain of one or more pointers to a history buffer, and a spill counter; and one or more logic elements, including at least one hardware logic element, comprising a data compressor to: inspect a string0 comprising n bytes at position p in a data file; get the spill counter from a hash entry corresponding to string0; inspect a string1 comprising n bytes at p+k, wherein k is a positive integer; get the spill counter from a hash entry corresponding to string1; determine that the spill counter for string1 is less than the spill counter for string0; and search a chain1 (the hash chain of a hash entry corresponding to string1) for a matching string of size at least n+k with an offset of −k.

    SQL SCAN HARDWARE ACCELERATOR
    158.
    发明申请
    SQL SCAN HARDWARE ACCELERATOR 审中-公开

    公开(公告)号：US20190188132A1

    公开(公告)日：2019-06-20

    申请号：US15845271

    申请日：2017-12-18

    Applicant: Intel Corporation

    Inventor： Kirk Yap ,  James D. Guilford ,  Simon N. Peffers ,  Vinodh Gopal

    IPC: G06F12/084 ,  G06F17/30 ,  G06F13/16 ,  G06F3/06

    CPC classification number: G06F12/084 ,  G06F3/0629 ,  G06F13/1652 ,  G06F13/1668 ,  G06F16/2453 ,  G06F2212/621

    Abstract: Various systems and methods for hardware acceleration circuitry are described. In an embodiment, circuitry is to perform 1-bit comparisons of elements of variable M-bit width aligned to N-bit width, where N is a power of 2, in a data path of P-bit width. Second and subsequent scan stages use the comparison results from the previous stage to perform 1-bit comparison of adjacent results, so that each subsequent stage results in a full comparison of element widths double that of the previous stage. A total number of stages required to scan, or filter, M-bit elements in N-bit width lanes is equal 1+log 2(N), and the total number of stages required for implementation in the circuitry is 1+log 2(P), where P is the maximum width of the data path comprising 1 to P elements.

    Keyed-hash message authentication code processors, methods, systems, and instructions
    160.
    发明授权
    Keyed-hash message authentication code processors, methods, systems, and instructions 有权

    公开(公告)号：US10313129B2

    公开(公告)日：2019-06-04

    申请号：US14751881

    申请日：2015-06-26

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  Jason W. Brandt

    IPC: H04L9/32 ,  G06F21/64 ,  G09C1/00 ,  G06F9/30

    Abstract: A processor of an aspect includes a decode unit to decode a keyed-hash message authentication code instruction. The keyed-hash message authentication code instruction is to indicate a message, to indicate at least one value that is to represent at least one of key information and key indication information, and to indicate a destination storage location. An execution unit is coupled with the decode unit. The execution unit, in response to the keyed-hash message authentication code instruction, is to store a message authentication code corresponding to the message in the destination storage location. The message authentication code is to be consistent with a keyed-hash message authentication code algorithm that is to use a cryptographic hash algorithm. The message authentication code is to be based on a cryptographic key associated with the at least one value. Other processors, methods, systems, and instructions are disclosed.

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