公开(公告)号：US20220336494A1

公开(公告)日：2022-10-20

申请号：US17854393

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11519 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11565

Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11476332B2

公开(公告)日：2022-10-18

申请号：US16890296

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L29/08 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: Some embodiments include an integrated assembly having a source structure. The source structure includes, in ascending order, a first conductively-doped semiconductor material, one or more first insulative layers, a second conductively-doped semiconductor material, one or more second insulative layers, and a third conductively-doped semiconductor material. The source structure includes blocks extending through the second conductively-doped semiconductor material. Conductive levels are over the source structure. Channel material extends vertically along the conductive levels, and extends into the source structure to be in direct contact with the second conductively-doped semiconductor material. One or more memory cell materials are between the channel material and the conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220278051A1

公开(公告)日：2022-09-01

申请号：US17187481

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L23/532 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528

Abstract: A microelectronic device comprises a stack structure, a staircase structure, composite pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The composite pad structures are on the steps of the staircase structure. Each of the composite pad structures comprises a lower pad structure, and an upper pad structure overlying the lower pad structure and having a different material composition than the lower pad structure. The conductive contact structures extend through the composite pad structures and to the conductive structures of the stack structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11411021B2

公开(公告)日：2022-08-09

申请号：US16890726

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11519 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11565

Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. The first deck has first memory cell levels, and the second deck has second memory cell levels. A pair of cell-material-pillars pass through the first and second decks. Memory cells are along the first and second memory cell levels. The cell-material-pillars are a first pillar and a second pillar. An intermediate level is between the first and second decks. The intermediate level includes a region between the first and second pillars. The region includes a first segment adjacent the first pillar, a second segment adjacent the second pillar, and a third segment between the first and second segments. The first and second segments include a first composition, and the third segment includes a second composition different from the first composition. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220246635A1

公开(公告)日：2022-08-04

申请号：US17164671

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220246536A1

公开(公告)日：2022-08-04

申请号：US17162269

申请日：2021-01-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough ,  Jordan D. Greenlee

IPC: H01L23/532 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/18 ,  H01L23/522 ,  H01L21/768

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the first memory region, the intermediate region and the second memory region. The panel is between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the first memory region, the second memory region and the intermediate region, and is directly adjacent the panel. The doped-semiconductor-material is at least part of conductive source structures within the first and second memory regions. Insulative rings surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220238444A1

公开(公告)日：2022-07-28

申请号：US17658907

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20220230962A1

公开(公告)日：2022-07-21

申请号：US17666093

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Travis Rampton ,  Everett Allen McTeer ,  Rita J. Klein

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11582 ,  H01L23/532 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528

Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

公开(公告)号：US20220149066A1

公开(公告)日：2022-05-12

申请号：US17091238

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli ,  Alyssa N. Scarbrough

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/3215

Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

公开(公告)号：US20220059569A1

公开(公告)日：2022-02-24

申请号：US17517459

申请日：2021-11-02

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.