公开(公告)号：US20250113545A1

公开(公告)日：2025-04-03

申请号：US18833507

申请日：2023-01-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO

IPC: H10D30/67 ,  H10B12/00 ,  H10D86/40

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor and a second transistor over an insulating surface; the first transistor and the second transistor share a metal oxide and a first conductor over the metal oxide; the first transistor includes a second conductor and a first insulator over the metal oxide and a third conductor over the first insulator; the second transistor includes a fourth conductor and a second insulator over the metal oxide and a fifth conductor over the second insulator; the first insulator is positioned in a region between the first conductor and the second conductor; the metal oxide and the third conductor overlap with each other with the first insulator therebetween; the second insulator is positioned in a region between the first conductor and the fourth conductor; and the metal oxide and the fifth conductor overlap with each other with the second insulator therebetween.

公开(公告)号：US20250081425A1

公开(公告)日：2025-03-06

申请号：US18950567

申请日：2024-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Takahiko ISHIZU ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: H10B12/00 ,  G11C5/02 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4094 ,  H01L27/12 ,  H01L29/786

Abstract: A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

公开(公告)号：US20240250182A1

公开(公告)日：2024-07-25

申请号：US18624513

申请日：2024-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/78696 ,  H10B12/31

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

公开(公告)号：US20230113155A1

公开(公告)日：2023-04-13

申请号：US17937823

申请日：2022-10-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yosuke TSUKAMOTO ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Yoshiaki OIKAWA ,  Kensuke YOSHIZUMI

IPC: G02B27/00 ,  G02B27/01

Abstract: Provided is a multifunctional display device or a multifunctional electronic device. Provided is a display device or electronic device with high visibility. Provided is a display device or electronic device with low power consumption. The electronic device includes a housing, a display device, a system unit, a camera, a secondary battery, a reflective surface, and a wearing tool. The system unit and the secondary battery are each positioned inside the housing. The system unit includes a charging circuit unit. The charging circuit unit is configured to control charging of the secondary battery. The system unit is configured to perform first processing based on imaging data of the camera. The first processing includes at least one of gesture operation, head tracking, and eye tracking. The system unit is configured to generate image data based on the first processing. The display device is configured to display the image data.

公开(公告)号：US20220415893A1

公开(公告)日：2022-12-29

申请号：US17891248

申请日：2022-08-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/13 ,  H01L27/115 ,  H01L29/786

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

公开(公告)号：US20220293159A1

公开(公告)日：2022-09-15

申请号：US17829579

申请日：2022-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Hajime KIMURA ,  Atsushi MIYAGUCHI ,  Tatsunori INOUE

IPC: G11C11/405 ,  H01L27/12 ,  H01L27/108 ,  G06F12/0893

Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

公开(公告)号：US20220108985A1

公开(公告)日：2022-04-07

申请号：US17424664

申请日：2019-11-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Takahiko ISHIZU ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

公开(公告)号：US20220085019A1

公开(公告)日：2022-03-17

申请号：US17419745

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Tatsuya ONUKI ,  Tomoaki ATSUMI ,  Kiyoshi KATO

IPC: H01L27/108 ,  H01L21/8239 ,  H01L29/786 ,  G11C29/52

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

公开(公告)号：US20220077199A1

公开(公告)日：2022-03-10

申请号：US17401360

申请日：2021-08-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

IPC: H01L27/12 ,  G02F1/1362 ,  H01L27/32 ,  H01L33/52

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic is insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching, to expose an active layer of the TFT.

公开(公告)号：US20220068967A1

公开(公告)日：2022-03-03

申请号：US17422883

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/24 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.