公开(公告)号：US20250056786A1

公开(公告)日：2025-02-13

申请号：US18723731

申请日：2022-12-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Ryota HODO ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: H10B12/00

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor; the transistor includes an oxide, a first conductor and a second conductor over the oxide, a first insulator that is placed over the first conductor and the second conductor and includes a first opening and a second opening, a second insulator in the first opening of the first insulator, and a third conductor over the second insulator; the first opening in the first insulator includes a region overlapping with the oxide; the third conductor includes a region overlapping with the oxide with the second insulator therebetween; the capacitor includes the second conductor, a third insulator in the second opening of the first insulator, and a fourth conductor over the third insulator; and the distance between the first conductor and the second conductor is smaller than the width of the first opening in a cross-sectional view of the transistor in a channel length direction.

公开(公告)号：US20250008721A1

公开(公告)日：2025-01-02

申请号：US18706096

申请日：2022-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Rihito WADA ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: H10B12/00

Abstract: A small semiconductor device is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a p-channel first transistor containing silicon in a channel formation region. The second layer includes an n-channel second transistor containing a metal oxide in a channel formation region. The first transistor and the second transistor form a CMOS circuit. A channel length of the first transistor is longer than a channel length of the second transistor.

公开(公告)号：US20240402994A1

公开(公告)日：2024-12-05

申请号：US18683540

申请日：2022-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Tatsuya ONUKI ,  Atsushi MIYAGUCHI ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI

IPC: G06F7/523 ,  G06F7/50 ,  G11C11/405 ,  H10B12/00

Abstract: An electronic device with a novel structure is provided. In an electronic device including a semiconductor device, the semiconductor device includes a CPU, an accelerator, and a memory device. The CPU includes a scan flip-flop circuit and a backup circuit electrically connected to the scan flip-flop circuit. The backup circuit includes a first transistor. The accelerator includes an arithmetic circuit and a data retention circuit electrically connected to the arithmetic circuit. The data retention circuit includes a second transistor. The memory device includes a memory cell including a third transistor. The first transistor to the third transistor each include a semiconductor layer containing a metal oxide in a channel formation region.

公开(公告)号：US20240332262A1

公开(公告)日：2024-10-03

申请号：US18740603

申请日：2024-06-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L25/065 ,  G11C5/06 ,  H01L23/00 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L29/78693 ,  H10B12/315 ,  H10B12/50 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

公开(公告)号：US20240331641A1

公开(公告)日：2024-10-03

申请号：US18293869

申请日：2022-07-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI

IPC: G09G3/3266 ,  G06F3/042 ,  G06V40/13 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G06F3/042 ,  G06V40/1318 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2354/00 ,  G09G2360/14

Abstract: To provide a display apparatus with a novel structure. A display portion including a first subpixel, a second subpixel, a first gate line supplied with a first selection signal to scan the first subpixel, and a second gate line supplied with a second selection signal to scan the second subpixel; and a driver control circuit including a gate line driver circuit, a switching portion that allots the first selection signal or the second selection signal output from the gate line driver circuit to the first gate line or the second gate line to be output, and a timing control circuit that controls the switching portion are included. The timing control circuit allows the gate line driver circuit to output the first selection signal of a first frame frequency and the second selection signal having a selection period longer than the first selection signal in a first operation mode, and to output the first selection signal and the second selection signal with a second frame frequency lower than the first frame frequency in a second operation mode.

公开(公告)号：US20240321205A1

公开(公告)日：2024-09-26

申请号：US18569779

申请日：2022-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Susumu KAWASHIMA ,  Yutaka OKAZAKI

IPC: G09G3/3233 ,  H01L27/088 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L27/088 ,  H01L27/1225 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2330/021

Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

公开(公告)号：US20240268092A1

公开(公告)日：2024-08-08

申请号：US18638994

申请日：2024-04-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Yuto YAKUBO ,  Seiya SAITO

IPC: H10B12/00 ,  G11C5/06 ,  G11C8/08 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H10B12/00 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  G11C5/06 ,  G11C8/08

Abstract: A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.

公开(公告)号：US20240122028A1

公开(公告)日：2024-04-11

申请号：US18274810

申请日：2022-02-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Hisao IKEDA ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: H10K59/65 ,  A61B3/00 ,  A61B3/12 ,  A61B3/14 ,  H10K59/90 ,  H10K59/95

CPC classification number: H10K59/65 ,  A61B3/005 ,  A61B3/12 ,  A61B3/14 ,  H10K59/90 ,  H10K59/95 ,  H01L24/05

Abstract: An object of one embodiment of the present invention is to provide a novel display device or a display system. Another object of one embodiment of the present invention is to provide a display device or a display system which can be manufactured at low cost and can provide various functions to a user. A pixel includes light-emitting elements whose emission colors are different from each other, a light-emitting element IR, a light-receiving element PS, and an infrared light sensor IRS. An image of a fundus of an eye is captured using the light-emitting element emitting an infrared light as a light source, and imaging is performed by the light-receiving element IRS. A substrate of a display panel is manufactured using a single crystal Si substrate capable of microfabrication and higher integration.

公开(公告)号：US20230410738A1

公开(公告)日：2023-12-21

申请号：US18036221

申请日：2021-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Tatsuya ONUKI

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2310/08 ,  G09G2300/0814 ,  G09G2330/021 ,  G09G2330/10 ,  G09G2320/0626

Abstract: A display device excellent in downsizing, reduction in power consumption, or layout flexibility of an arithmetic device is provided. The display device includes a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for performing display in the pixel circuit. The functional circuit includes a CPU including a CPU core including a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer includes the driver circuit and the CPU. The second layer includes the pixel circuit and the backup circuit. The first layer includes a semiconductor layer including silicon in a channel formation region. The second layer includes a semiconductor layer including a metal oxide in a channel formation region. The CPU has a function of correcting the image signal in accordance with the amount of current flowing through the pixel circuit.

公开(公告)号：US20230335180A1

公开(公告)日：2023-10-19

申请号：US18206117

申请日：2023-06-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.