Abstract:
A method and system for providing an event driven hardfile image in a computer system is disclosed. The computer system includes a hardfile, a hardfile adapter, a master boot record and an operating system. The method and system include providing an extended physical partition table describing a plurality of partitions on the hardfile and defining at least one image using a utility. Each image corresponds to at least a portion of the plurality of partitions and to a corresponding event. An image is to be mapped to the master boot record in response to an occurrence of the corresponding event. The method and system also include providing an event driven table including each of the at least one image.
Abstract:
A method and system for controlling the addition of a USB device to a host computer system via a hardware hot plug detector that monitors USB ports. The differential signal lines connecting to the USB device are logically OR'ed together, such that logically high D+ or D− signals from the USB device signal a central processing unit's (CPU) system management interrupt (SMI) line to initiate system management mode (SMM). Entering SMM transfers control of the host computer system to an SMI Interrupt Handler BIOS, which resides in the SMM address space of the hose computer system. The SMM BIOS is loaded into the SMM address space during Power On Self Test (POST) and is secured prior to booting the Operating System (OS). The SMM BIOS code contains instructions as to whether or not the connected USB device should be made visible to the operating system of the computer. If the device is not authorized, it is disabled, the D+/D− lines are not connected to the USB host controller, and the SMI signal is cleared, allowing the computer to continue operation without the operating system ever being aware of the USB device.
Abstract:
A computer system contains selectively available boot block codes. A first boot block is of the conventional type and is stored in storage media such as flash ROM on a system planar with the processor of the computer system. A second boot block is located on a feature card and contains an immutable security code in compliance with the Trusted Computing Platform Alliance (TCPA) specification. The boot block on the feature card is enabled if the first boot block detects the presence of the feature card. The computer system can be readily modified as the computer system is reconfigured, while maintaining compliance with the TCPA specification. A switching mechanism controls which of the boot blocks is to be activated. The feature card is disabled in the event of a computer system reset to prevent access to the TCPA compliant code and function.
Abstract:
A method and system for providing correct operational parameters for up-level design components utilized within a computer system after a low level basic input/output system (BIOS) code has been qualified. A patch file is created or obtained for a component that is added to a computer system after a BIOS code has been qualified for the computer system. The patch file includes the operating parameters (or profiles) of the component. The flash module is designed with a memory block reserved for holding data from the patch file, which can be updated independently of the rest of the flash module. The Advance Configuration Program Interface (ACPI) or advanced power management (APM) code of the computer system is modified to dynamically read the parameters from this memory block and update their respective functions accordingly. During set up of the computer system, the patch file is flashed into the reserved block of the flash module. The data is merged by the FLASH utility into the existing BIOS so that the computer system has the correct parameters for the particular component.
Abstract:
A method, computer program product and system for reducing the boot time of a TCPA based computing system. A flash memory in the TCPA based computing system may include a register comprising bits configured to indicate whether the segments of the flash memory have been updated. The flash memory may further include a table configured to store measurements of the segments of the flash memory. The flash memory may further include a boot block code that includes a Core Root of Trust for Measurement (CRTM). The CRTM may read the bits in the register to determine if any of the segments of the flash memory have been updated. The CRTM may further obtain the measurement values in the table for those segments that store the POST BIOS code that have not been updated thereby saving time from measuring the POST BIOS code and consequently reducing the boot time.
Abstract:
A method and system are disclosed for substituting an anonymous media access controller (MAC) address for a client computer system's real MAC address in order to disguise an identity of the client computer system when the client computer system is utilizing a network. The client computer system is coupled to a server computer system via the network. A primary storage device is established for storing a MAC address. A MAC address which is stored in the primary storage device is utilized as a network address for the client computer system when the client computer system is utilizing the network. An anonymous MAC address is generated. The anonymous MAC address is not associated with any particular client computer system. The anonymous MAC address is then stored in the primary storage device. The client computer system utilizes the anonymous MAC address as the network address for the client computer system when the client computer system is utilizing the network.
Abstract:
A secure write blocking circuit and method of operation thereof. The secure write blocking circuit includes enable and disable block input terminals coupled to a blocking circuit. The blocking circuit, such as a set/reset latch in a preferred embodiment, generates a block signal to prevent write access to a nonvolatile memory device, such as flash memory, in response to signals provided to the enable and disable input terminals. The secure write blocking circuit also includes an interrupt generator, coupled to the disable block input terminal, that generates an interrupt signal in response to a signal at the disable input terminal. In a related embodiment the secure write blocking circuit also includes a logic circuit, coupled to the blocking circuit, that receives the block signal and a write enable signal and in response thereto generates a control signal to a write enable input of the nonvolatile memory device.
Abstract:
A data processing system and method including a docking station and a portable computer capable of being coupled to the docking station are disclosed for securing the docking station, the portable computer, and for securing the attachment of the docking station to the portable computer. The portable computer is coupled to the docking station. A disconnection password is established. When the portable computer is disconnected from the docking station, a user is prompted for the disconnection password. The portable computer is disabled in response to a failure to correctly enter the disconnection password, wherein the portable computer is inoperable without a correct entry of the disconnection password. When a portable computer is connected to the docking station, a correct entry of a connection password is required. In response to a failure to correctly enter the connection password, access to the docking station is prohibited. When the docking station is physically removed from its stationary support, correct entry of a relocation password is required. In response to a failure to correctly enter the password, access to the docking station is prohibited.
Abstract:
Disclosed is a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD), a random access memory (RAM), and a LAN controller. A flash memory module is coupled to the CPU and an input/output (IO) bus and includes a basic input output system (BIOS) stored therein. The BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The BIOS is further operative on completion of the POST for transferring a portion of BIOS from the module to the RAM and for transferring control of the of the computer system to the BIOS portion. The portion of BIOS is operative to load a protected mode operating system (OS) into RAM and transfer control to the OS. The system further includes a logic circuit coupled to the flash memory module and the IO bus. A communication subsystem is coupled to the IO bus, the logic circuit and the flash memory for allowing the remote computer to access the BIOS in flash memory while the protected mode OS is running.
Abstract:
A client on a network is provided with auxiliary low power logic, at the network adaptor, that is always active and simulates network traffic (e.g., Ethernet format) normally sent under control of the main client system processor(s). This logic collects client status information and reports to the network manager, irrespective of the system's CPU power level, information and provides for interaction between the user and the administration or network manager to exercise broader control and perform repair and upgrades which would otherwise require a dialog with the user and/or limit repair and reconfiguration of the client system to off-hours activity. The auxiliary logic also can receive and interpret commands from the network that conform to a predefined format.