公开(公告)号：US20200278806A1

公开(公告)日：2020-09-03

申请号：US16288361

申请日：2019-02-28

Applicant: Silicon Motion Inc.

Inventor： Chao-Kuei Hsieh

IPC: G06F3/06

Abstract: The present disclosure provides a Universal Flash Storage (UFS) memory module including an input/output interface, a flash memory, and a controller. The flash memory includes: a write buffer portion; and a normal storage portion having a plurality of logic units. The controller includes: a processor; a first register indicating a maximum size of the write buffer portion; a second register indicating an available size of the write buffer portion; and a third register. If the third register indicates the UFS memory module is in a shared buffer mode, the write buffer portion only includes a first shared buffer area. If the third register indicates the UFS memory module is in an advanced mode, the write buffer portion includes at least one dedicated buffer area, each corresponding to one of the plurality of logic units. The present disclosure also provides a controller, an electronic device and a method for operating a UFS memory module.

公开(公告)号：US20200272561A1

公开(公告)日：2020-08-27

申请号：US16585583

申请日：2019-09-27

Applicant: Silicon Motion, Inc.

Inventor： Jian-Yu CHEN ,  Bo-Yan JHAN ,  Yuh-Jang LO ,  Shih-Chang CHANG

IPC: G06F12/02

Abstract: A high-performance data storage device is disclosed. A non-volatile memory stores a logical-to-physical address mapping table that maps logical addresses recognized by a host to a physical space in the non-volatile memory. The logical-to-physical address mapping table is divided into a plurality of sub mapping tables. A memory controller utilizes temporary storage when controlling the non-volatile memory. The memory controller plans a sub mapping table area in the temporary storage to store sub mapping tables corresponding to a plurality of nodes which are linked and managed by multiple linked lists.

公开(公告)号：US20200272330A1

公开(公告)日：2020-08-27

申请号：US15930675

申请日：2020-05-13

Applicant: Silicon Motion, Inc.

Inventor： Shu-Lei CHEN ,  Ming-Hung CHANG

IPC: G06F3/06

Abstract: An optimized non-volatile memory operating method. A data storage device has a plurality of non-volatile memory spaces, a plurality of command queues, and a controller. The command queues are provided to correspond to the non-volatile memory spaces one on one. The controller adds task switching commands into the command queues. The non-volatile memory spaces are operated through the same channel. The sharing of the same channel between the non-volatile memory spaces is optimized by the task switching commands.

公开(公告)号：US20200266998A1

公开(公告)日：2020-08-20

申请号：US16869562

申请日：2020-05-07

Applicant: Silicon Motion, Inc.

Inventor： Ching-Ke Chen ,  Yu-Han Hsiao

IPC: H04L9/32 ,  H04L9/14 ,  H04L9/08 ,  G06F3/06 ,  G06F21/62 ,  G06F21/57

Abstract: A data storage device including a non-volatile memory and a micro-controller is provided. The non-volatile memory stores a firmware file. The micro-controller is coupled to the non-volatile memory, and performs an encryption procedure on the firmware file. The encryption procedure includes: using a first key and a first algorithm to encrypt the firmware file to generate a signature, using the first key and a second algorithm to scramble the signature to generate a scrambled signature, and attaching the scrambled signature to the firmware file.

公开(公告)号：US20200264894A1

公开(公告)日：2020-08-20

申请号：US16869956

申请日：2020-05-08

Applicant: Silicon Motion, Inc.

Inventor： Chien-Chung CHUNG ,  Mei-Ting LIN ,  Chen-Ning YANG

IPC: G06F9/4401

Abstract: A data storage device waking up from a sleep mode rapidly is disclosed. The data storage device uses a controller to operate a non-volatile memory. The controller has a microprocessor and a volatile memory. The microprocessor loads boot code from the non-volatile memory to a not-always-on area of the volatile memory according to a script loaded on an always-on area of the volatile memory. The microprocessor executes the boot code loaded on the not-always-on area to load an in-system program from the non-volatile memory to the not-always-on area for execution of the in-system program. The script loaded on the always-on area is loaded from the non-volatile memory, and the non-volatile memory is searched to load the script to the always-on area in response to powering on a data storage device containing the non-volatile memory from a power-off state.

公开(公告)号：US20200264778A1

公开(公告)日：2020-08-20

申请号：US16278182

申请日：2019-02-18

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Wen-Long Wang

IPC: G06F3/06

Abstract: A method for performing data-compression management in a storage server may include: receiving data from a host device; performing entropy detection on a plurality of sets of partial data to generate entropy detection values of the plurality of sets of partial data, respectively; classifying the plurality of sets of partial data according to the entropy detection values of the plurality of sets of partial data, respectively, to perform data compression on at least one portion of the plurality of sets of partial data through a plurality of data compression modules, respectively, wherein the plurality of data compression modules correspond to different compression capabilities, respectively; and storing the plurality of sets of partial data into at least one storage device of the storage server and recording address mapping information of the plurality of sets of partial data, respectively. An associated apparatus is also provided.

公开(公告)号：US20200256913A1

公开(公告)日：2020-08-13

申请号：US16548463

申请日：2019-08-22

Applicant: SILICON MOTION, INC.

Inventor： Wei-Liang Sung

IPC: G01R31/28 ,  G11C11/412 ,  G06F3/06

Abstract: The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

公开(公告)号：US20200242024A1

公开(公告)日：2020-07-30

申请号：US16683191

申请日：2019-11-13

Applicant: Silicon Motion, Inc.

Inventor： Jian-Dong Du ,  Chia-Jung Hsiao ,  Tsung-Chieh Yang

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/4093

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

公开(公告)号：US20200241795A1

公开(公告)日：2020-07-30

申请号：US16257022

申请日：2019-01-24

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Wen-Long Wang

IPC: G06F3/06 ,  G06F12/02

Abstract: A method for performing access management of a memory device and associated apparatus (e.g. the memory device and controller thereof such as a memory controller within the memory device, an associated host device and an associated electronic device) are provided. The method may include: when the host device sends a host command to the memory device, utilizing the memory controller to estimate a completion time of the host command, to generate completion time information corresponding to the completion time; and utilizing the memory controller to send the completion time information to the host device, to allow the host device to perform polling after the completion time to obtain execution result of the host command.

公开(公告)号：US10719254B2

公开(公告)日：2020-07-21

申请号：US16039722

申请日：2018-07-19

Applicant: Silicon Motion, Inc.

Inventor： Wen-Sheng Lin ,  Yu-Da Chen

IPC: G06F3/06

Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. The memory blocks include single-level cell blocks and multiple-level cell blocks. The controller is coupled to the memory device. When the controller executes a predetermined procedure to write data stored in the single-level cell blocks into the multiple-level cell blocks, the controller is configured to determine whether a valid page count corresponding to each single-level cell block is greater than a threshold, and when the valid page count corresponding to more than one single-level cell block is greater than the threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks.