公开(公告)号：US08132408B2

公开(公告)日：2012-03-13

申请号：US11987528

申请日：2007-11-30

Applicant: Bin Li ,  Mustafa Taha Al-Shawaf ,  Rishabh Sinha ,  Deepak Bhupendrabhai Thakkar

Inventor： Bin Li ,  Mustafa Taha Al-Shawaf ,  Rishabh Sinha ,  Deepak Bhupendrabhai Thakkar

IPC: F02B33/44 ,  F02B33/00 ,  F24B1/06 ,  F28F1/02 ,  F28F13/12 ,  F28F1/34

CPC classification number: F02B29/0462 ,  F28D7/005 ,  F28F1/02 ,  F28F1/34 ,  F28F3/02 ,  Y02T10/146

Abstract: An air-to-fluid intercooler is disclosed. The air-to-fluid intercooler may include a core assembly including an outer circumference and an inner circumference, at least one annular tube body configured to direct flow of a cooling fluid within the core assembly, and at least one curved fin coupled to an exterior surface of the at least one annular tube body and configured to direct a flow of charge air through the core assembly.

Abstract translation: 公开了一种空气 - 液体中间冷却器。 空气到流体中间冷却器可以包括包括外圆周和内圆周的芯组件，至少一个环形管体构造成引导芯组件内的冷却流体的流动，以及耦合到外部的至少一个弯曲翅片 所述至少一个环形管体的表面并且构造成引导加压空气流通过所述芯组件。

公开(公告)号：USD648792S1

公开(公告)日：2011-11-15

申请号：US29382831

申请日：2011-01-07

Applicant: Bin Li

Designer： Bin Li

公开(公告)号：US08059454B2

公开(公告)日：2011-11-15

申请号：US12531851

申请日：2008-12-01

Applicant: Bin Li ,  Adam Matthew Bumgarner ,  Daniel Pirkl ,  George Michael

Inventor： Bin Li ,  Adam Matthew Bumgarner ,  Daniel Pirkl ,  George Michael

IPC: G11C7/00

CPC classification number: G11C29/02 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0092

Abstract: An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write “0” and write “1” pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write “0” and write “1” pulse signals into a second set of continuous write “0” and write “1” pulse signals. The single pulse generator subsequently converts the second set of continuous write “0” and write “1” pulse signals into a single write “0” pulse signal or a single write “1” pulse signal when programming the chalcogenide memory cell.

Abstract translation: 公开了一种可调写入脉冲发生器。 可调写脉冲发生器包括带隙参考电流，可编程环形振荡器，分频器和单脉冲发生器。 带隙参考电流电路在编程硫属化物存储器单元所需的温度的预定范围内产生良好补偿的电流。 可编程环形振荡器基于良好补偿的电流产生第一组连续写入“0”和写入“1”脉冲信号。 分频器然后将第一组连续写入“0”和“1”脉冲信号分成第二组连续写“0”和写“1”脉冲信号。 当编程硫族化物存储单元时，单脉冲发生器随后将第二组连续写入“0”和“1”脉冲信号转换为单个写入“0”脉冲信号或单个写入“1”脉冲信号。

公开(公告)号：US07989085B2

公开(公告)日：2011-08-02

申请号：US12275315

申请日：2008-11-21

Applicant: Bin Li ,  Chao-Hsun Lin ,  Jen-Lung Huang ,  Xian-Liang Liu ,  Gui-Yun Yang

Inventor： Bin Li ,  Chao-Hsun Lin ,  Jen-Lung Huang ,  Xian-Liang Liu ,  Gui-Yun Yang

IPC: B21D39/00 ,  B32B15/00

CPC classification number: H04M1/0283 ,  Y10T428/12444 ,  Y10T428/12486 ,  Y10T428/12639 ,  Y10T428/12993

Abstract: An exemplary housing of electronic device includes a metallic main body and a metallic three-dimensional woven member formed on at least a part of a surface of the metallic main body. An electronic device using the housing is also provided. The housing of the electronic device has a textured touching feeling.

Abstract translation: 电子设备的示例性壳体包括形成在金属主体的表面的至少一部分上的金属主体和金属三维织造构件。 还提供了使用该外壳的电子设备。 电子设备的外壳具有纹理触感。

公开(公告)号：US07965541B2

公开(公告)日：2011-06-21

申请号：US12525458

申请日：2008-11-25

Applicant: Bin Li ,  John C. Rodgers ,  Nadim F. Haddad

Inventor： Bin Li ,  John C. Rodgers ,  Nadim F. Haddad

IPC: G11C11/00

CPC classification number: G11C11/4125 ,  G11C13/0004 ,  G11C14/009

Abstract: A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.

Abstract translation: 公开了一种非易失性单事件镦粗（SEU）容错锁存器。 非易失性SEU容限锁存器包括以交叉耦合方式彼此连接的第一和第二反相器。 第一反相器内的晶体管的栅极通过第一反馈电阻连接到第二反相器内的晶体管的漏极。 类似地，第二反相器内的晶体管的栅极经由第二反馈电阻器连接到第一反相器内的晶体管的漏极。 非易失性SEU容限锁存器还包括连接到逆变器的一对硫族化物存储元件，用于存储信息。

公开(公告)号：USD628634S1

公开(公告)日：2010-12-07

申请号：US29353761

申请日：2010-01-13

Applicant: Bin Li

Designer： Bin Li

公开(公告)号：US20100141296A1

公开(公告)日：2010-06-10

申请号：US12595865

申请日：2008-12-10

Applicant: Neil Wood ,  David Rea ,  Bin Li

Inventor： Neil Wood ,  David Rea ,  Bin Li

IPC: H03K19/003 ,  H03K19/094

CPC classification number: H03K19/23

Abstract: A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

Abstract translation: 电流模式逻辑选择电路包括三个双输入分频NOR门。 每个双输入分频NOR门接收相应的输入信号对，并根据输入信号产生一对第一输出信号。 三输入分频NOR门耦合到双输入分频NOR门以接收第一输出信号，并响应于来自双输入分频NOR门的第一输出信号产生第二对输出信号。 两个和三个输入的分频NOR门可以由电流模式逻辑缓冲电路形成，并且在一个实施例中，在三输入分频NOR门中，缓冲电路被硬化。

公开(公告)号：US20100091981A1

公开(公告)日：2010-04-15

申请号：US12422677

申请日：2009-04-13

Applicant: Yun-Qing Shi ,  Bin Li

Inventor： Yun-Qing Shi ,  Bin Li

IPC: H04K1/00 ,  G06K9/00

CPC classification number: G06T1/0028 ,  G06T2201/0051 ,  G06T2201/0052 ,  G06T2201/0061 ,  G06T2201/0201

Abstract: Techniques described herein are generally related to steganalysis of suspect media. Steganalysis techniques may include receiving instances of suspect media as input for steganalytic processing. A first set of quantized blocks of data elements may be identified within the media, with this first set of blocks being eligible to be embedded with steganographic data. A second set of quantized blocks of data elements may be identified within the media, with this second set of blocks being ineligible to be embedded with steganographic data. The steganalysis techniques may requantize the first and second blocks. In turn, these techniques may compare statistics resulting from requantizing the first block with statistics resulting from requantizing the second block. The steganalysis techniques may then assess whether the first block of data elements is embedded with steganographic features based on how the statistics of the second blocks compare with the statistics of the first blocks.

Abstract translation: 本文描述的技术通常涉及可疑介质的隐写分析。 隐匿分析技术可以包括接收可疑媒体的实例作为隐写处理的输入。 可以在媒体内识别数据元素的第一组量化块，其中该第一组块有资格嵌入隐写数据。 可以在媒体内识别第二组数据元素的量化块，其中第二组块不符合隐写数据​​的嵌入。 隐写分析技术可以重新调整第一和第二块。 反过来，这些技术可以将从重新量化第一个块得到的统计数据与由再量化第二个块产生的统计数据进行比较。 隐写分析技术可以基于第二块的统计数据如何与第一块的统计量进行比较来评估第一块数据元素是否嵌入隐写特征。

公开(公告)号：US20100074000A1

公开(公告)日：2010-03-25

申请号：US12525510

申请日：2008-11-26

Applicant: Bin Li ,  Adam Matthew Bumgarner

Inventor： Bin Li ,  Adam Matthew Bumgarner

IPC: G11C7/00 ,  G11C11/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C27/005 ,  G11C29/026 ,  G11C29/1201 ,  G11C29/50 ,  G11C2013/0054 ,  G11C2029/5006

Abstract: An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.

Abstract translation: 公开了一种用于表征硫族化物存储器单元的模拟存取电路。 模拟访问电路包括模拟访问控制模块，地址和数据控制模块以及模拟单元访问和电流监控模块。 模拟访问控制模块选择性地控制是否应该在特定的硫族化物存储器单元上执行正常存储器存取或模拟存储器访问。 地址和数据控制模块允许根据输入地址对硫属化物存储器单元进行正常存储器访问。 模拟电池接入和电流监测模块根据输入地址对硫族化物存储单元进行模拟存储器存取，并监测来自与硫族化物存储单元相关联的读出放大器的参考电流。

公开(公告)号：US20100067620A1

公开(公告)日：2010-03-18

申请号：US12565284

申请日：2009-09-23

Applicant: Alexander Reznik ,  Rui Yang ,  Bin Li ,  Ariela Zeira

Inventor： Alexander Reznik ,  Rui Yang ,  Bin Li ,  Ariela Zeira

IPC: H04L27/06

CPC classification number: H04L25/0242 ,  H04B1/71052 ,  H04L25/0212 ,  H04L25/03057 ,  H04L25/03292 ,  H04L2025/03426 ,  H04L2025/03509 ,  H04L2025/03605

Abstract: A method and apparatus for use in data estimation in wireless communication are provided. A wireless communications signal is received and transformed to produce a received vector. The received vector is processed using a sliding window based approach that includes processing each of a plurality of windows. For each window, an approximate circulant channel response matrix is produced for use in estimating a data vector corresponding to the window.

Abstract translation: 提供了一种用于无线通信中的数据估计的方法和装置。 无线通信信号被接收和变换以产生接收的矢量。 使用基于滑动窗口的方法处理接收的向量，其包括处理多个窗口中的每一个。 对于每个窗口，产生近似循环通道响应矩阵用于估计对应于该窗口的数据矢量。