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    NARROW CONDUCTIVE STRUCTURES FOR GATE CONTACT OR TRENCH CONTACT
    161.
    发明申请
    NARROW CONDUCTIVE STRUCTURES FOR GATE CONTACT OR TRENCH CONTACT 有权

    公开(公告)号：US20220393007A1

    公开(公告)日：2022-12-08

    申请号：US17340747

    申请日：2021-06-07

    Applicant: Intel Corporation

    Inventor： Leonard P. GULER ,  Mohit K. HARAN ,  Tahir GHANI ,  Charles H. WALLACE

    IPC: H01L29/417 ,  H01L27/088

    Abstract: Narrow conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric liner is along the plurality of dielectric spacers over the plurality of gate structures. A plurality of conductive pin structures is between the dielectric liner, individual ones of the plurality of conductive pin structures on corresponding ones of the plurality of gate structures.

    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES
    163.
    发明申请
    ISOLATION SCHEMES FOR GATE-ALL-AROUND TRANSISTOR DEVICES 有权

    公开(公告)号：US20220246759A1

    公开(公告)日：2022-08-04

    申请号：US17722142

    申请日：2022-04-15

    Applicant: Intel Corporation

    Inventor： Rishabh MEHANDRU ,  Stephen M. CEA ,  Biswajeet GUHA ,  Tahir GHANI ,  William HSU

    IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

    STACKED THIN FILM TRANSISTORS WITH NANOWIRES
    164.
    发明申请
    STACKED THIN FILM TRANSISTORS WITH NANOWIRES 有权

    公开(公告)号：US20220208991A1

    公开(公告)日：2022-06-30

    申请号：US17695744

    申请日：2022-03-15

    Applicant: Intel Corporation

    Inventor： Seung Hoon SUNG ,  Abhishek A. SHARMA ,  Van H. LE ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Tahir GHANI

    IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

    Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

    RECESSED THIN-CHANNEL THIN-FILM TRANSISTOR
    167.
    发明申请
    RECESSED THIN-CHANNEL THIN-FILM TRANSISTOR 有权

    公开(公告)号：US20220029025A1

    公开(公告)日：2022-01-27

    申请号：US17496690

    申请日：2021-10-07

    Applicant: Intel Corporation

    Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Yih WANG

    IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

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