公开(公告)号：US07910432B2

公开(公告)日：2011-03-22

申请号：US12393509

申请日：2009-02-26

申请人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.

摘要翻译： 每个存储器串包括：在垂直方向上延伸到衬底的第一柱状半导体层; 多个第一导电层，其形成为夹着具有电荷陷阱层的绝缘层并以二维方式扩展; 第二柱状半导体层，其与所述第一柱状半导体层的顶表面接触并且在垂直方向上延伸到所述衬底; 以及多个第二导电层，其形成为与第二柱状半导体层夹着绝缘层，并且形成为沿与垂直方向正交的第一方向延伸的条纹图案。 多个第一导电层的第一方向的端部相对于彼此分步地形成，多个第二导电层的整体形成在第一导电层的顶层的正上方的区域中， 并且多个第一导电层和多个第二导电层被与多个第一导电层和第二导电层连续形成的保护绝缘层覆盖。

公开(公告)号：US07902591B2

公开(公告)日：2011-03-08

申请号：US12244989

申请日：2008-10-03

申请人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7923 ,  H01L29/7926

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：在垂直于衬底的方向上延伸的存储器柱状半导体; 与记录柱状半导体接触的隧道绝缘层; 与隧道绝缘层接触并积累电荷的电荷累积层; 与电荷累积层接触的块绝缘层; 以及与块绝缘层接触的多个存储器导电层。 电荷累积层的下部被隧道绝缘层和块绝缘层覆盖。

公开(公告)号：US20110033995A1

公开(公告)日：2011-02-10

申请号：US12908546

申请日：2010-10-20

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/336

CPC分类号： H01L21/764 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578

摘要： A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.

摘要翻译： 非易失性半导体存储装置具有多个具有串联连接的多个电可重写存储单元的存储器串。 每个存储器串包括：沿垂直方向延伸到衬底的第一柱状半导体层; 电荷累积层，经由第一绝缘层形成在第一柱状半导体层周围; 以及经由第二绝缘层形成在电荷累积层周围的第一导电层。 每个第一导电层被形成为以二维方式膨胀，并且在位于其上方和下方的第一导电层之间形成气隙。

公开(公告)号：US20110018052A1

公开(公告)日：2011-01-27

申请号：US12820371

申请日：2010-06-22

申请人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括堆叠结构，半导体柱，存储层和外部绝缘膜。 堆叠结构包括沿第一方向交替堆叠的多个电极膜和多个电极间绝缘膜。 半导体柱沿第一方向刺穿层叠结构。 存储层设置在电极膜和半导体柱之间。 外绝缘膜设置在电极膜和存储层之间。 该装置包括第一区域和第二区域。 沿着与第一区域的第一方向垂直的第二方向的外绝缘膜的外径大于第二区域的外径。 第一区域中沿着第二方向的外绝缘膜的厚度比第二区域厚。

公开(公告)号：US07868416B2

公开(公告)日：2011-01-11

申请号：US12773038

申请日：2010-05-04

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/93 ,  H01L21/76

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/7923 ,  H01L29/7926

摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.

摘要翻译： 半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体 与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且 漏极区域与主体部分连接。

公开(公告)号：US20100327340A1

公开(公告)日：2010-12-30

申请号：US12821551

申请日：2010-06-23

申请人： Shigeto OOTA ,  Yoshimasa Mikajiri ,  Masaru Kito ,  Ryouhei Kirisawa

发明人： Shigeto OOTA ,  Yoshimasa Mikajiri ,  Masaru Kito ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括层叠结构单元，半导体柱，存储层，内绝缘膜，外绝缘膜和帽绝缘膜。 该单元包括在多个电极间绝缘膜上沿第一方向交替堆叠的多个电极膜。 支柱沿第一方向刺穿层叠的结构单元。 存储层设置在电极膜和半导体柱之间。 内部绝缘膜设置在存储层和半导体柱之间。 外绝缘膜设置在存储层和电极膜之间。 帽绝缘膜设置在外绝缘膜和电极膜之间，并且帽绝缘膜具有比外绝缘膜更高的相对介电常数。

公开(公告)号：US07859066B2

公开(公告)日：2010-12-28

申请号：US12140734

申请日：2008-06-17

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： H01L21/8247

CPC分类号： H01L27/105 ,  H01L21/02161 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31645 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.

摘要翻译： 非易失性半导体存储器件具有多个存储串，每个存储串包括串联连接的多个电可重写存储器单元。 存储器串包括从基板沿垂直方向延伸的柱状半导体部分，与柱状半导体部分相邻形成并构成为积蓄电荷的第一电荷存储层，与第一电荷存储层相邻形成的第一块绝缘体， 第一导体与第一块绝缘体相邻形成。

公开(公告)号：US20100276743A1

公开(公告)日：2010-11-04

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理，以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US07737041B2

公开(公告)日：2010-06-15

申请号：US12059280

申请日：2008-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Takayuki Okamura

发明人： Masaru Kito ,  Hideaki Aochi ,  Takayuki Okamura

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11524

摘要： A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.

摘要翻译： 半导体器件包括半导体层，该半导体层包括在第一方向上延伸的多个平行的线性直线部分。 该层还包括多个连接部分，每个连接部分具有在第一方向上的宽度，足以在其中形成可接线的触点，并且布置成在第二方向上在相邻的直部分之间连接。 连接部具有与平行于第二方向的第一直线对准的各自的端部。

公开(公告)号：US07732891B2

公开(公告)日：2010-06-08

申请号：US12132181

申请日：2008-06-03

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Yasuyuki Matsuoka

IPC分类号： H01L29/93 ,  H01L21/76

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/7923 ,  H01L29/7926

摘要： A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section.

摘要翻译： 半导体器件具有衬底，形成在衬底的表面部分上的源极区域，形成在衬底上的第一绝缘层，形成在第一绝缘层上的栅电极，形成在栅电极上的第二绝缘层，主体 与源极区域连接，穿过第一绝缘层，栅电极和第二绝缘层，并且包含空隙，围绕主体部分的栅极绝缘膜，并且形成在主体部分和栅电极之间，并且 漏极区域与主体部分连接。