公开(公告)号：US08198667B2

公开(公告)日：2012-06-12

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US20100276743A1

公开(公告)日：2010-11-04

申请号：US12808321

申请日：2008-12-25

申请人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Takuji Kuniya ,  Yosuke Komori ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L29/792 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7926

摘要： A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

摘要翻译： 通过在硅衬底上交替层叠多个电介质膜和电极膜来形成层叠体。 接下来，在层叠体中形成在层叠方向上延伸的贯通孔。 接下来，进行选择性氮化处理，以在对应于电极膜的通孔的内表面的区域中选择性地形成由氮化硅制成的电荷层。 接下来，进行高压氧化处理，以在电荷层和电极膜之间形成由氧化硅制成的阻挡层。 接下来，在通孔的内侧表面上形成由氧化硅制成的隧道层。 因此，可以制造其中为每个电极膜分裂电荷层的快闪存储器。

公开(公告)号：US08649217B2

公开(公告)日：2014-02-11

申请号：US13418516

申请日：2012-03-13

申请人： Takuji Kuniya ,  Katsunori Yahashi

发明人： Takuji Kuniya ,  Katsunori Yahashi

IPC分类号： G11C11/34

CPC分类号： H01L27/2481 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1675

摘要： According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.

摘要翻译： 根据一个实施例，存储单元部分包括存储层，其中非易失性存储单元布置在第一布线的交叉位置和被第一布线和第二布线夹在第二布线之间。 第一绘图部分将存储单元部分和第一接触部分与第一布线连接，第二绘图部分将第二接线部分连接到存储单元部分和第二接触部分。 虚拟图案设置在与构成第一和第二绘图部分的第一和第二布线正下方的存储层相对应的层中。

公开(公告)号：US08729667B2

公开(公告)日：2014-05-20

申请号：US13609679

申请日：2012-09-11

申请人： Takuji Kuniya

发明人： Takuji Kuniya

IPC分类号： H01L29/06

CPC分类号： H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1675

摘要： According to one embodiment, a second electrode layer is formed on first structures where a first electrode layer and a first memory cell layer sequentially stacked above a substrate are patterned in a line-and-space shape extending in a first direction and a first interlayer insulating film embedded between the first structures. Etching is performed from the second electrode layer to a predetermined position in an inner portion of the first memory cell layer by using a first mask layer having a line-and-space pattern extending in a second direction, so that a first trench is formed. A first modifying film is formed on a side surface of the first trench, anisotropic etching is performed on the first memory cell layer by using the first mask layer, and after that, isotropic etching is performed.

摘要翻译： 根据一个实施例，在第一结构上形成第二电极层，其中顺序地堆叠在基板上的第一电极层和第一存储单元层以沿第一方向延伸的线空间形状和第一层间绝缘 电影嵌入在第一个结构之间。 通过使用具有沿第二方向延伸的线间距图案的第一掩模层，从第二电极层到第一存储单元层的内部的预定位置进行蚀刻，从而形成第一沟槽。 在第一沟槽的侧表面上形成第一修饰膜，通过使用第一掩模层在第一存储单元层上进行各向异性蚀刻，然后进行各向同性蚀刻。

公开(公告)号：US08399322B2

公开(公告)日：2013-03-19

申请号：US13189977

申请日：2011-07-25

申请人： Takuji Kuniya

发明人： Takuji Kuniya

IPC分类号： H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.

摘要翻译： 非易失性半导体存储器件包括多个存储单元，每个存储单元包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在半导体衬底上的浮置栅极，包括第一绝缘膜，第二绝缘层 形成在浮动栅极上的膜，以及形成在浮动栅极上并包含第二绝缘膜的控制栅极; 元件隔离绝缘膜，形成在所述半导体衬底中并且沿栅极长度方向延伸以隔离在栅极宽度方向上相邻的存储单元; 以及形成在元件隔离绝缘膜上和在栅极宽度方向上相邻的浮动栅极之间的气隙。

公开(公告)号：US08008149B2

公开(公告)日：2011-08-30

申请号：US12119981

申请日：2008-05-13

申请人： Takuji Kuniya

发明人： Takuji Kuniya

IPC分类号： H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.

摘要翻译： 非易失性半导体存储器件包括多个存储单元，每个存储单元包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在半导体衬底上的浮置栅极，包括第一绝缘膜，第二绝缘层 形成在浮动栅极上的膜，以及形成在浮动栅极上并包含第二绝缘膜的控制栅极; 元件隔离绝缘膜，形成在所述半导体衬底中并且沿栅极长度方向延伸以隔离在栅极宽度方向上相邻的存储单元; 以及形成在元件隔离绝缘膜上和在栅极宽度方向上相邻的浮动栅极之间的气隙。

公开(公告)号：US07986001B2

公开(公告)日：2011-07-26

申请号：US12275944

申请日：2008-11-21

申请人： Takuji Kuniya

发明人： Takuji Kuniya

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11543

摘要： A semiconductor memory device comprises: a plurality of transistors having a stacked-gate structure, each transistor including a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a silicide suppression region between the aperture and the gate insulator to suppress diffusion of metal atoms from the silicided upper gate.

摘要翻译： 半导体存储器件包括：多个晶体管，具有堆叠栅极结构，每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，栅极绝缘体 形成在下栅极上，并且在栅极绝缘体插入的下栅极上形成并硅化的上栅极。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括在孔和栅极绝缘体之间的硅化物抑制区域，以抑制金属原子从硅化上栅极的扩散。

公开(公告)号：US20110147942A1

公开(公告)日：2011-06-23

申请号：US12838960

申请日：2010-07-19

申请人： Katsunori YAHASHI ,  Takuji Kuniya ,  Takaya Matsushita ,  Murato Kawai ,  Shuichi Taniguchi

发明人： Katsunori YAHASHI ,  Takuji Kuniya ,  Takaya Matsushita ,  Murato Kawai ,  Shuichi Taniguchi

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： A method of manufacturing a semiconductor memory device of an embodiment includes: after forming a first interconnection layer and a memory cell layer above a semiconductor substrate, forming first lines by forming first grooves extending in first direction; forming a thin film on the side walls of the first grooves; forming a stack structure by filling an interlayer insulating film in the first grooves; forming a second interconnection layer above the stack structure; forming second lines by forming second grooves extending in second direction; removing the thin film exposed at bottom of the second grooves; and forming columnar memory cells by removing the memory cell layer exposed at bottom of the second grooves. The thin film has higher etching rate than the interlayer insulating film, and is removed prior to portions of the memory cell layer adjoining the thin film.

摘要翻译： 制造实施例的半导体存储器件的方法包括：在半导体衬底之上形成第一互连层和存储单元层之后，通过形成沿第一方向延伸的第一沟槽来形成第一线; 在第一槽的侧壁上形成薄膜; 通过在第一槽中填充层间绝缘膜形成堆叠结构; 在所述堆叠结构之上形成第二互连层; 通过形成沿第二方向延伸的第二凹槽形成第二线; 去除在第二凹槽的底部暴露的薄膜; 以及通过去除在第二凹槽的底部暴露的存储单元层来形成柱状存储单元。 薄膜具有比层间绝缘膜更高的蚀刻速率，并且在与薄膜邻接的存储单元层的部分之前被去除。

公开(公告)号：US20090191712A1

公开(公告)日：2009-07-30

申请号：US12208010

申请日：2008-09-10

申请人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

发明人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L21/308

CPC分类号： H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

摘要： In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.

摘要翻译： 在本发明的一个方面中，制造半导体器件的方法可以包括在待图案化的非晶硅层上形成第一膜，第一膜和非线性膜的线间距比约为3:1 ，在对第一膜进行处理之后，将该图案的线部分从线部分的两个纵向侧线直到线部分的宽度减小到大约三分之一，在下一步处理之后，将非晶硅层的一部分重新形成第一膜 不能使重整部分具有不同的蚀刻比，并除去除了重整部分以外的第一膜和非晶硅层。

公开(公告)号：US08546196B2

公开(公告)日：2013-10-01

申请号：US13018722

申请日：2011-02-01

申请人： Takuji Kuniya ,  Kotaro Noda

发明人： Takuji Kuniya ,  Kotaro Noda

IPC分类号： H01L21/768 ,  G11C11/21

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： According to one embodiment, a non-volatile memory device is formed as described below. First, a wiring material layer, which configures a part of a wiring of an element, is stacked above an element layer, the wiring material layer is processed in a predetermined shape, and the element layer is etched using the wiring material layer as a mask. Next, an insulation layer is embedded between etched patterns, and the insulation layer is removed using the wiring material layer as a stopper. Then, a wiring layer, which is in contact with the wiring material layer, is formed on the insulation layer from which the wiring material layer is exposed.

摘要翻译： 根据一个实施例，如下所述形成非易失性存储器件。 首先，将构成元件的布线的一部分的布线材料层层叠在元件层的上方，将布线材料层加工成规定的形状，使用布线材料层作为掩模蚀刻元件层 。 接下来，在蚀刻图案之间嵌入绝缘层，并且使用布线材料层作为塞子去除绝缘层。 然后，在布线材料层露出的绝缘层上形成与布线材料层接触的布线层。