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公开(公告)号：US20220189551A1
公开(公告)日：2022-06-16
申请号：US17685219
申请日：2022-03-02
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
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公开(公告)号：US20220172782A1
公开(公告)日：2022-06-02
申请号：US17108783
申请日：2020-12-01
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Anna Maria Conti , Innocenzo Tortorelli
Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.
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公开(公告)号：US20220093166A1
公开(公告)日：2022-03-24
申请号：US17488186
申请日：2021-09-28
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Karthik Sarpatwari , Innocenzo Tortorelli , Nevil N. Gajera
IPC: G11C11/406 , G11C11/4074 , G11C11/4076 , G11C11/409
Abstract: Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device).
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公开(公告)号：US20220068391A1
公开(公告)日：2022-03-03
申请号：US17005928
申请日：2020-08-28
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Mattia Boniardi , Mattia Robustelli
Abstract: Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.
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公开(公告)号：US11120870B2
公开(公告)日：2021-09-14
申请号：US16998240
申请日：2020-08-20
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
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Patent Agency Ranking
公开(公告)号：US20210264972A1
公开(公告)日：2021-08-26
申请号：US16797432
申请日：2020-02-21
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Hari Giduturi , Fabio Pellizzer
IPC: G11C11/56 , G11C11/409 , G11C11/4074 , G11C29/50
Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.
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公开(公告)号：US11094377B2
公开(公告)日：2021-08-17
申请号：US16711361
申请日：2019-12-11
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20210134885A1
公开(公告)日：2021-05-06
申请号：US17144669
申请日：2021-01-08
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US20210027813A1
公开(公告)日：2021-01-28
申请号：US16518876
申请日：2019-07-22
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Richard K. Dodge , Innocenzo Tortorelli , Mattia Robustelli , Mario Allegra
IPC: G11C7/10
Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
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公开(公告)号：US20210005257A1
公开(公告)日：2021-01-07
申请号：US17024248
申请日：2020-09-17
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
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