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    Integrated assemblies, and methods of forming integrated assemblies
    162.
    发明授权
    Integrated assemblies, and methods of forming integrated assemblies 有权

    公开(公告)号：US10886282B2

    公开(公告)日：2021-01-05

    申请号：US16831355

    申请日：2020-03-26

    Applicant: Micron Technology, Inc.

    Inventor： Amirhasan Nourbakhsh ,  John K. Zahurak ,  Sanh D. Tang ,  Silvia Borsari ,  Hong Li

    IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78

    Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

    Method Of Forming An Array Of Capacitors, A Method Of Forming DRAM Circuitry, And A Method Of Forming An Elevationally-Elongated Conductive Structure Of Integrated Circuitry
    166.
    发明申请
    Method Of Forming An Array Of Capacitors, A Method Of Forming DRAM Circuitry, And A Method Of Forming An Elevationally-Elongated Conductive Structure Of Integrated Circuitry 审中-公开

    公开(公告)号：US20200020694A1

    公开(公告)日：2020-01-16

    申请号：US16578608

    申请日：2019-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Kuo-Chen Wang ,  Sanh D. Tang

    IPC: H01L27/108 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias individually having an upper horizontal perimeter. The conductive vias individually have an upper horizontal perimeter. Masking material is formed directly above the conductive vias. An opening is formed in the masking material directly above individual of the upper horizontal perimeters of individual of the conductive vias. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Individual of the masking-material openings comprise a lower horizontal perimeter that overlaps the upper horizontal perimeter of the conductive via directly there-below. Conductive material is formed in the individual masking-material openings against sidewalls of the individual masking-material openings and directly against the conductive via directly there-below. An upper horizontal perimeter of the conductive material in the individual masking-material openings extends outwardly beyond the upper horizontal perimeter of the conductive via directly there-below.

    SEMICONDUCTOR DEVICES COMPRISING SILVER
    168.
    发明申请
    SEMICONDUCTOR DEVICES COMPRISING SILVER 审中-公开

    公开(公告)号：US20190363253A1

    公开(公告)日：2019-11-28

    申请号：US16538477

    申请日：2019-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

    IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

    Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry
    169.
    发明授权
    Elevationally-elongated conductive structure of integrated circuitry, method of forming an array of capacitors, method of forming DRAM circuitry, and method of forming an elevationally-elongated conductive structure of integrated circuitry 有权

    公开(公告)号：US10461149B1

    公开(公告)日：2019-10-29

    申请号：US16021683

    申请日：2018-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Kuo-Chen Wang

    IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/108

    Abstract: A method of forming elevationally-elongated conductive structures of integrated circuitry comprises providing a substrate comprising a plurality of spaced elevationally-extending conductive vias. Conductive material is formed directly above and directly against the conductive vias. The conductive material has an upper surface and a first sidewall that are directly above individual of the conductive vias in a vertical cross-section. The conductive material has a second sidewall that is not directly above the individual conductive vias. Covering material is formed directly above individual of the upper surfaces and against individual of the first sidewalls directly above the individual conductive vias. The covering material comprises a composition different from that of at least some of the conductive material. Etching is conducted completely through at least some of the covering material that is directly above the individual upper surfaces to the conductive material directly there-below and etching is conducted into said conductive material. The covering material that is against the individual first sidewalls masks the individual first sidewalls from being etched during said etchings. Structure that may be independent of method is disclosed.

    Semiconductor devices including silver conductive materials
    170.
    发明授权
    Semiconductor devices including silver conductive materials 有权

    公开(公告)号：US10411186B2

    公开(公告)日：2019-09-10

    申请号：US15848399

    申请日：2017-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

    IPC: H01L45/00 ,  H01L21/768 ,  H01L23/532

    Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

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