公开(公告)号：US20230075949A1

公开(公告)日：2023-03-09

申请号：US17550835

申请日：2021-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alexander Martin

IPC: H01L29/735 ,  H01L29/423 ,  H01L29/45 ,  H01L29/10 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region composed of semiconductor material; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and an extrinsic base contact wrapping around the semiconductor material of the extrinsic base region.

公开(公告)号：US20230073958A1

公开(公告)日：2023-03-09

申请号：US18055576

申请日：2022-11-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michal Rakowski ,  Petar I. Todorov ,  Yusheng Bian ,  Won Suk Lee ,  Asif J. Chowdhury ,  Kenneth J. Giewont

IPC: G02B6/125 ,  G02F1/01

Abstract: Disclosed is a photonic structure and associated method. The structure includes a closed-curve waveguide having a first height, as measured from the top surface of an insulator layer, and an outer curved sidewall that extends essentially vertically the full first height (e.g., to minimize signal loss). The structure includes a closed-curve thermal coupler and a heating element. The closed-curve thermal coupler is thermally coupled to and laterally surrounded by the closed-curve waveguide and has a second height that is less than the first height. In some embodiments, the closed-curve waveguide and the closed-curve thermal coupler are continuous portions of the same semiconductor layer having different thicknesses. The heating element is thermally coupled to the closed-curve thermal coupler and thereby indirectly thermally coupled to the closed-curve waveguide. Thus, the heating element is usable for thermally tuning the closed-curve waveguide via the closed-curve thermal coupler to minimize any temperature-dependent resonance shift (TDRS).

公开(公告)号：US20230064512A1

公开(公告)日：2023-03-02

申请号：US17456395

申请日：2021-11-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Alvin J. Joseph ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/15 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a superlattice layer and methods to form the same. The bipolar transistor structure may have a semiconductor layer of a first single crystal semiconductor material over an insulator layer. The semiconductor layer includes an intrinsic base region having a first doping type. An emitter/collector (E/C) region may be adjacent the intrinsic base region and may have a second doping type opposite the first doping type. A superlattice layer is on the E/C region of the semiconductor layer. A raised E/C terminal, including a single crystal semiconductor material, is on the superlattice layer. The superlattice layer separates the E/C region from the raised E/C terminal.

公开(公告)号：US20230063900A1

公开(公告)日：2023-03-02

申请号：US17524438

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Man Gu ,  Jagar Singh ,  Haiting Wang ,  Jeffrey Johnson

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737 ,  H01L29/06

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

公开(公告)号：US20230062747A1

公开(公告)日：2023-03-02

申请号：US17529002

申请日：2021-11-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Haiting Wang ,  Jagar Singh

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/735 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.

公开(公告)号：US20230061219A1

公开(公告)日：2023-03-02

申请号：US17509384

申请日：2021-10-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20230056457A1

公开(公告)日：2023-02-23

申请号：US17445461

申请日：2021-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Shashank S. Nemawarkar

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

公开(公告)号：US11588056B2

公开(公告)日：2023-02-21

申请号：US16992440

申请日：2020-08-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Jagar Singh

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate.

公开(公告)号：US20230047046A1

公开(公告)日：2023-02-16

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/146 ,  H01L29/06 ,  H01L21/84

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20230034728A1

公开(公告)日：2023-02-02

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.