公开(公告)号：US20090237971A1

公开(公告)日：2009-09-24

申请号：US12367213

申请日：2009-02-06

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/00

CPC classification number: G11C5/063 ,  G11C5/02 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal.

Abstract translation: 半导体存储器件包括控制器，多个衬底以及在每个衬底上间隔开并且顺序的多个堆叠存储器。 每个堆叠的存储器包括连接到相应基板的接口芯片和堆叠在接口芯片上的多个存储器芯片。 控制器被配置为控制堆叠的存储器。 接口芯片被配置为通过介于控制器和命令信号所指向的所选择的堆叠存储器之间的堆叠存储器的顺序中的每个接口芯片从控制器转发命令信号。 接口芯片可以将命令信号从其中一个衬底上的堆叠存储器的序列的一端转发到所选择的堆叠存储器，并且将来自所选择的堆叠存储器的响应信号通过剩余的堆叠存储器按顺序在衬底上转发 返回到控制器或通过命令信号拍摄的相同的堆叠存储器序列。

公开(公告)号：US07586546B2

公开(公告)日：2009-09-08

申请号：US11268623

申请日：2005-11-08

Applicant: Jung-bae Lee ,  Jae-hong Park

Inventor： Jung-bae Lee ,  Jae-hong Park

IPC: H04N5/66

CPC classification number: G09G5/003 ,  G09G2310/0229 ,  G09G2320/08 ,  H04N5/21 ,  H04N5/44513 ,  H04N7/012 ,  H04N21/4402 ,  H04N21/485

Abstract: A display apparatus having a display. The display apparatus includes a video signal processor having a processor to process an input video signal and a picture quality improving part to improve picture quality of the processed video signal. The video signal processor processes the video signal through a path that includes a signal processing path to selectively bypass the picture quality improving part. The display apparatus further includes a selection input part through which the user selects a bypass mode corresponding to the signal processing path. Finally, the display apparatus has a controller controlling the video signal processor to output the video signal processed through the processor to the display after bypassing the picture quality improving part when the user selects the bypass mode through the selection input part. Thus, the picture quality improving function may be omitted to thereby reduce signal processing time.

Abstract translation: 具有显示器的显示装置。 显示装置包括具有处理输入视频信号的处理器和图像质量改善部分的视频信号处理器，以改善处理的视频信号的图像质量。 视频信号处理器通过包括信号处理路径的路径处理视频信号，以选择性地绕过图像质量改善部分。 显示装置还包括选择输入部，用户通过该选择输入部选择与信号处理路径对应的旁路模式。 最后，当用户通过选择输入部分选择旁路模式时，显示装置具有控制视频信号处理器以将通过处理器处理的视频信号输出到显示器的旁路图像质量改善部分之后的控制器。 因此，可以省略图像质量改善功能，从而减少信号处理时间。

公开(公告)号：US07551514B2

公开(公告)日：2009-06-23

申请号：US11836283

申请日：2007-08-09

Applicant: Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

Inventor： Sang-yun Kim ,  Jung-bae Lee ,  Young-don Choi

IPC: G11C8/00

CPC classification number: G11C7/1006

Abstract: A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation mode. The first operation mode codes the data of the first through nth data groups such that the counted number of data bits in a first logic state is minimized. The second operation mode codes the data of the first through nth data groups such that the difference between the number of data bits and flag information bits in the first and second logic state are minimized. This prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

Abstract translation: 一种在初始操作中利用数据编码方法的半导体存储器件。 该装置包括对数据位数和标志信息数据位进行计数的多个计数器。 数据编码单元选择性地应用第一和第二操作模式。 第一操作模式对第一至第n数据组的数据进行编码，使得在第一逻辑状态中的计数的数据位数最小化。 第二操作模式对第一至第n数据组的数据进行编码，使得第一和第二逻辑状态中的数据位数和标志信息位之间的差最小化。 这样可防止数据的初始逻辑状态由于器件的初始操作中的电压降而被改变。

公开(公告)号：US20090147559A1

公开(公告)日：2009-06-11

申请号：US12326940

申请日：2008-12-03

Applicant: Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

Inventor： Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

IPC: G11C11/4091 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

Abstract translation: 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

公开(公告)号：US20090085650A1

公开(公告)日：2009-04-02

申请号：US12325846

申请日：2008-12-01

Applicant: Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

Inventor： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

IPC: G05F3/02

CPC classification number: G05F1/465

Abstract: An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

Abstract translation: 提供内部电压产生电路。 半导体器件的内部电压产生电路包括：控制信号发生电路，用于根据多个数据位产生控制信号;比较器，用于将参考电压与内部电压进行比较，以在控制信号失效时产生驱动信号 ，用于当所述控制信号被激活时使所述驱动信号失活的驱动信号控制电路和用于接收外部电源电压并且响应于所述驱动信号产生所述内部电压的内部电压驱动电路。 因此，可以根据半导体器件的数据输入和/或输出位的数量将内部电压转换为参考电压电平或外部电源电压，并且即使当数据输入和/或输出位数 增加，可以提高数据访问速度。

公开(公告)号：US20080273623A1

公开(公告)日：2008-11-06

申请号：US12103823

申请日：2008-04-16

Applicant: Hoe-ju CHUNG ,  Jung-bae LEE

Inventor： Hoe-ju CHUNG ,  Jung-bae LEE

IPC: H04L27/00

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US20080208537A1

公开(公告)日：2008-08-28

申请号：US12037324

申请日：2008-02-26

Applicant: Jung-Bae LEE ,  Ki-Chul CHUN

Inventor： Jung-Bae LEE ,  Ki-Chul CHUN

IPC: G06F15/00

CPC classification number: G11C29/50 ,  G11C29/50012 ,  G11C2029/1206

Abstract: A circuit measuring the operating speed of a semiconductor memory chip in relation to a defined asynchronous access time is disclosed. The circuit includes a test signal path extending between a test input pad and a test output pad and is formed by a plurality of test signal path segments and at least one delay element associated with at least one of the plurality of test signal path segments, such that a delay time for a test signal communicated through the test signal path is indicative of the actual asynchronous access time for the semiconductor memory chip. Each one of the plurality of test signal path segments is either an interior test signal path segment or an exterior test signal path segment.

Abstract translation: 公开了相对于定义的异步访问时间测量半导体存储器芯片的操作速度的电路。 电路包括在测试输入焊盘和测试输出焊盘之间延伸的测试信号路径，并且由多个测试信号路径段和与多个测试信号路径段中的至少一个相关联的至少一个延迟元件形成， 通过测试信号路径传送的测试信号的延迟时间表示半导体存储器芯片的实际异步访问时间。 多个测试信号路径段中的每一个是内部测试信号路径段或外部测试信号路径段。

公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

Applicant: Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

Inventor： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

Abstract translation: 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US07219274B2

公开(公告)日：2007-05-15

申请号：US10831702

申请日：2004-04-23

Applicant: Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

Inventor： Jung-Bae Lee ,  Hoe-Ju Chung ,  Byung-Se So

IPC: G11C29/04 ,  G11C29/48

CPC classification number: G11C29/14 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/2602

Abstract: A memory module, including a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.

Abstract translation: 一种存储器模块，包括用于写入和读取m位并行数据的多个半导体存储器件; 以及用于将n位串行数据转换成m位并行数据以输出到多个半导体存储器件的缓冲器，将m位并行数据转换成n位串行数据，以在第一外部部分输出 正常操作，缓冲2n位并行数据以输出到多个半导体存储器件，以及在测试操作期间缓冲m位并行数据以输出到第二外部部分。

公开(公告)号：US07200067B2

公开(公告)日：2007-04-03

申请号：US10895554

申请日：2004-07-21

Applicant: Mee-Hyun Ahn ,  Jung-Bae Lee

Inventor： Mee-Hyun Ahn ,  Jung-Bae Lee

IPC: G11C9/00

CPC classification number: H01L23/50 ,  G11C5/025 ,  G11C2207/105 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.

Abstract translation: 一种半导体存储器件，包括能够减少用于在单元阵列中读取和写入数据的数据路径的控制焊盘和输入/输出I / O焊盘，以及用于驱动半导体存储器件的方法。 半导体存储器件包括布置在存储器芯片的单元区域的多个存储器组，以及多个控制焊盘和多个I / O焊盘，这些控制焊盘和多个I / O焊盘在存储芯片处彼此分开布置，用于读/写数据 来自/在存储体中，其中多个控制焊盘和I / O焊盘分散在相邻存储体之间的周边区域和存储体的外部。