公开(公告)号：US20240056063A1

公开(公告)日：2024-02-15

申请号：US18492597

申请日：2023-10-23

Applicant: STMICROELECTRONICS SA

Inventor： Lionel Vogt

IPC: H03K5/00

CPC classification number: H03K5/00006

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

公开(公告)号：US20240048863A1

公开(公告)日：2024-02-08

申请号：US18482117

申请日：2023-10-06

Applicant: STMicroelectronics SA

Inventor： Valentin Rebiere ,  Antoine Drouot

IPC: H04N25/60 ,  H04N23/84 ,  H04N25/13 ,  H04N25/705

CPC classification number: H04N25/60 ,  H04N23/843 ,  H04N25/13 ,  H04N25/705

Abstract: An embodiment method for estimating a missing or incorrect value in a table of values generated by a photosite matrix comprises a definition of a zone of the table comprising the value to be estimated and other values, referred to as neighboring values, and an estimation of the value to be estimated based on the primary neighboring values and the weight associated with these primary neighboring values, wherein a weight of each neighboring value, referred to as primary neighboring value, of the same colorimetric component as that of the missing or incorrect value to be estimated, is determined according to differences between neighboring values disposed on an axis and neighboring values disposed parallel with this axis and positioned in relation to this axis on the same side as the primary neighboring value for which the weight is determined.

公开(公告)号：US11887982B2

公开(公告)日：2024-01-30

申请号：US17191250

申请日：2021-03-03

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0266 ,  H01L27/0277 ,  H01L27/0629 ,  H02H9/046 ,  H01L28/20

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US11886214B2

公开(公告)日：2024-01-30

申请号：US17393658

申请日：2021-08-04

Applicant: STMicroelectronics SA

Inventor： Lionel Vogt ,  Eoin Padraig O Hannaidh

IPC: G05F1/575 ,  G05F1/565

CPC classification number: G05F1/575 ,  G05F1/565

Abstract: A low-dropout regulator includes a power stage having an output terminal coupled to a load circuit operable in different operating modes in which it receives different output currents. An error amplifier has a first input coupled to a reference voltage and an output coupled to an input terminal of the power stage. A compensation circuit includes a first stage with an RC filter coupled to the input terminal of the power stage, and generating an initial compensation voltage. A second stage includes a first transistor coupled between a supply voltage and a second node, and controlled by a complementary control signal, a high-side capacitor coupled between the second node and ground, and a third transistor coupled between the initial compensation voltage and the second node, and controlled by a control signal representative of the current operating mode of the load circuit.

公开(公告)号：US20240023468A1

公开(公告)日：2024-01-18

申请号：US18190901

申请日：2023-03-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Alain FLEURY ,  Stephane MONFRAY ,  Philippe CATHELIN ,  Bruno REIG ,  Vincent PUYAL

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8613 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8828

Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.

公开(公告)号：US20240014809A1

公开(公告)日：2024-01-11

申请号：US18345726

申请日：2023-06-30

Applicant: STMicroelectronics SA

Inventor： Laurent Jean Garcia ,  Marc Houdebine

IPC: H03K3/03 ,  H03K5/1252

CPC classification number: H03K3/0315 ,  H03K5/1252

Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.

公开(公告)号：US20230350593A1

公开(公告)日：2023-11-02

申请号：US17733779

申请日：2022-04-29

Applicant: STMICROELECTRONICS SA

Inventor： Zouhaier AOUAINI ,  Haithem RAHMANI

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/0659 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0604

Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.

公开(公告)号：US20230297126A1

公开(公告)日：2023-09-21

申请号：US18119535

申请日：2023-03-09

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA ,  STMicroelectronics (Alps) SAS

Inventor： Alexandre TRAMONI ,  Florent SIBILLE ,  Patrick ARNOULD

IPC: G05F1/46 ,  H04B5/00

CPC classification number: G05F1/46 ,  H04B5/0037

Abstract: An electronic device includes a near-field communication module and a powering circuit for delivering a power supply voltage to the near-field communication module. When the near-field communication module is in a low power mode, the powering circuit is configured for an operational mode where it is periodically started to provide the power supply voltage.

公开(公告)号：US20230223989A1

公开(公告)日：2023-07-13

申请号：US18094309

申请日：2023-01-06

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA ,  STMicroelectronics Razvoj Polprevodnikov D.O.O.

Inventor： Alexandre TRAMONI ,  Kosta KOVACIC ,  Florent SIBILLE ,  Nicolas CORDIER ,  Anthony TORNAMBE ,  Jean Remi RUIZ ,  Guillaume JAUNET

IPC: H04B5/00

CPC classification number: H04B5/0025 ,  H04B5/0056

Abstract: A near-field communication circuit of a first NFC device alternates, in low power mode, between: first phases of emission of field bursts and second phases spanning an entire duration separating two successive first phases. Each second phase includes a field detector enabling phase. In one implementation, the field detector enabling phase extends all along a duration of the second phase. In an alternate implementation, the field detector enabling phase is interrupted by field detector disabling phases. Each field detector disabling phase has a duration shorter than a minimum duration of each first phase.

公开(公告)号：US20230163117A1

公开(公告)日：2023-05-25

申请号：US18095728

申请日：2023-01-11

Applicant: STMicroelectronics SA

Inventor： Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0277 ,  H01L27/1203 ,  H01L29/7436

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.